/* Copyright (c) 2022, Canaan Bright Sight Co., Ltd
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _ISP_COM_DEF_H_
#define _ISP_COM_DEF_H_

#include <stdlib.h>
#include <stdio.h>

//#define _FPGA

#ifndef OK
#define OK (0)
#endif

#ifndef SUCCESS
#define SUCCESS (0)
#endif

#ifndef FAILURE
#define FAILURE (1)
#endif

#ifndef NULL
   #define NULL      (0)
#endif

typedef enum{
    FALSE = 0,
    TRUE  = 1,
} BOOL;


typedef enum _SENSOR_TYPE
{
    NORMAL_SENSOR = 0,
    RGBIR_SENSOR  = 1,
    TOF_SENSOR    = 2,
}SENSOR_TYPE;

typedef enum _ISP_PIPE_WDR_MODE_E
{
	ISP_PIPE_WDR_NONE,
	ISP_PIPE_WDR_2_FRAME,
	ISP_PIPE_WDR_3_FRAME,
	ISP_PIPE_WDR_BUTT,
} ISP_PIPE_WDR_MODE_E;

typedef enum _ISP_PIPE_DOWN_STREAM_E
{
	ISP_PIPE_MAIN_OUT,
	ISP_PIPE_DS0_OUT,
	ISP_PIPE_DS1_OUT,
	ISP_PIPE_DS2_OUT,
} ISP_PIPE_DOWN_STREAM_E;

typedef enum _ISP_PIPE_MODE_E
{
	ISP_PIPE_MODE_4K = 0,
	ISP_PIPE_MODE_F2K,
	ISP_PIPE_MODE_R2K,
	ISP_PIPE_MODE_TOF,
	ISP_PIPE_MODE_BUTT
}ISP_PIPE_MODE_E;

typedef enum _ISP_PIPE_DRV_INT_MODE_E
{
	ISP_PIPE_DRV_INT_NORMAL,
	ISP_PIPE_DRV_INT_WDR_2_FRAME,
	ISP_PIPE_DRV_INT_WDR_3_FRAME,
	ISP_PIPE_DRV_INT_R2K,
	ISP_PIPE_DRV_INT_F2K_R2K,
	ISP_PIPE_DRV_INT_VI,
	ISP_PIPE_DRV_10_INT_VI,
	ISP_PIPE_DRV_INT_MODE_BUTT
}ISP_PIPE_DRV_INT_MODE_E;

//OSD
typedef enum _OSD_Layer_Type_E
{
    OSD_RGB_24BIT         = 0,
    OSD_MONOCHROME_8BIT   = 1,
    OSD_RGB_16BIT         = 2,
    OSD_RGB_32BIT         = 3,
    OSD_RGB_4444          = 4,
    OSD_RGB_1555            = 5,
}OSD_Layer_Type_E;

typedef enum _OSD_Dma_Ctl_E
{
    OSD_ORIGINAL_ORDER     = 0,
    OSD_TWO_BIT_ENDIAN    = 2,
    OSD_LITTLE_ENDIAN      = 3,
 }OSD_Dma_Ctl_E;

typedef enum _OSD_Dma_RGB_Rev
{
    OSD_RGB_REV_R     = 0,
    OSD_RGB_REV_B     = 1,
    OSD_RGB_REV_NUM   = 2,
 }OSD_Dma_RGB_Rev;

typedef enum _OSD_Alpha_Type_E
{
    OSD_FIXED_VALUE         = 0,  //Alpha data is a fixed value
    OSD_L2_ALPHA_ADDR       = 1,  //Alpha data is at alpha data block in L2_ALPHA_ADDR.
    OSD_INTERVAL_R          = 2,  //Alpha data interval is aligned with R channel of OSD
    OSD_INTERVAL_G          = 3,  //Alpha data interval is aligned with G channel of OSD
    OSD_INTERVAL_B          = 4,  //Alpha data interval is aligned with B channel of OSD
    OSD_INTERVAL_A          = 5   //Alpha data interval is aligned with Alpha Channel of OSD for OSD type is 3, 4, and 5
 }OSD_Alpha_Type_E;

typedef enum _VO_TEST_CASE_E
{
    CASE_UNDEFINE = 0,
	//
	LAYER2_420_DS0_1080x720_YUV420,
    //normal
    VO_CASE_LAYER0_420_1920x1080_1920x1080,
    VO_CASE_LAYER0_420_1920x1080_1920x1080_ENDIAN,
    VO_CASE_LAYER0_420_320352_ENDIAN,
    VO_CASE_LAYER0_420_1920x1080_1888x1048,
    VO_CASE_LAYER0_422_1920x1080_1280x720,
    VO_CASE_LAYER0_420_1920x1080_240x135,
    VO_CASE_LAYER1_420_1280x720,
    VO_CASE_LAYER2_420_1280x720,
    VO_CASE_LAYER3_420_1280x720,
    VO_CASE_I4_RGB888_512x200,
    VO_CASE_I5_RGB888_512x200,
    VO_CASE_I6_RGB888_512x200,
    VO_CASE_I4_ARGB8888_512x200,
    VO_CASE_I5_ARGB8888_512x200,
    VO_CASE_I6_ARGB8888_512x200,
    VO_CASE_ALL_VIDEO_LAYER_OSD1_MIX,
    VO_CASE_ALL_VIDEO_LAYER_OSD2_MIX,
    VO_CASE_ALL_VIDEO_LAYER_OSD3_MIX,

    LAYER0_420_1920x1080_1920x1080_YUV420,
    LAYER0_420_1920x1080_640x1080_YUV420,
    LAYER0_420_1920x1080_240x135_YUV420,
    LAYER0_420_1280x720_1280x720_YUV420,
    LAYER0_420_640x480_640x480_YUV420,
    LAYER0_420_320x240_320x240_YUV420,
    LAYER0_420_640x480_1280x720_YUV420,
    LAYER0_CROP_INPUT_TEST_YUV420_1280x720,
    LAYER0_CROP_INPUT_TEST_YUV420_64x64,
    LAYER0_OUTPUT_WINDOW_MOVE_YUV420,
    LAYER0_420_1920x1080_1920x1080_YUV422,
    LAYER0_420_1920x1080_1888x1048_YUV420,
    LAYER0_420_1920x1080_1280x720_YUV420,
    LAYER0_420_1920x1080_1080x720_YUV420,
    LAYER0_420_1920x1080_240x135_YUV422,
    LAYER0_420_1280x720_1920x1080_YUV422,
    LAYER0_420_640x480_1280x720_YUV422,
    LAYER0_CROP_INPUT_TEST_YUV422_1280x720,
    LAYER0_CROP_INPUT_TEST_YUV422_64x64,
    LAYER0_OUTPUT_WINDOW_MOVE_YUV422,
    LAYER0_420_STRIDE_TEST,
    LAYER0_422_STRIDE_TEST,
    LAYER0_420_640x1080_YUV420,
    LAYER1_420_1920x1080_YUV420,
    LAYER1_CROP_INPUT_TEST_YUV420,
    LAYER1_OUTPUT_WINDOW_MOVE_YUV420,
    LAYER1_420_1920x1080_YUV422,
    LAYER1_CROP_INPUT_TEST_YUV422,
    LAYER1_OUTPUT_WINDOW_MOVE_YUV422,
    LAYER1_420_STRIDE_TEST,
    LAYER1_422_STRIDE_TEST,
    LAYER1_420_832x1080_YUV420,
    LAYER1_420_640x1080_YUV420,
        
    LAYER2_420_1920x1080_YUV420,
    LAYER2_CROP_INPUT_TEST_YUV420,
    LAYER2_OUTPUT_WINDOW_MOVE_YUV420,
    LAYER2_420_1920x1080_YUV422,
    LAYER2_CROP_INPUT_TEST_YUV422,
    LAYER2_OUTPUT_WINDOW_MOVE_YUV422,
    LAYER2_420_STRIDE_TEST,
    LAYER2_422_STRIDE_TEST,
        
    LAYER3_420_1920x1080_YUV420,
    LAYER3_CROP_INPUT_TEST_YUV420,
    LAYER3_OUTPUT_WINDOW_MOVE_YUV420,
    LAYER3_420_1920x1080_YUV422,
    LAYER3_CROP_INPUT_TEST_YUV422,
    LAYER3_OUTPUT_WINDOW_MOVE_YUV422,
    LAYER3_420_STRIDE_TEST,
    LAYER3_422_STRIDE_TEST,

    OSD0_RGB888_GLOBAL_ALPHA,
    OSD0_RGB888_SEPARATE_ALPHA,
    OSD0_RGB565_GLOBAL_ALPHA,
    OSD0_RGB565_SEPARATE_ALPHA,
    OSD0_ARGB8888_GLOBAL_ALPHA,
    OSD0_ARGB8888_SEPARATE_ALPHA,
    OSD0_ARGB8888_PIXEL_ALPHA,
    OSD0_ARGB4444_GLOBAL_ALPHA,
    OSD0_ARGB4444_SEPARATE_ALPHA,
    OSD0_ARGB4444_PIXEL_ALPHA,
    OSD0_ARGB1555_GLOBAL_ALPHA,
    OSD0_ARGB1555_SEPARATE_ALPHA,
    OSD0_ARGB1555_PIXEL_ALPHA,
    OSD0_MONO8_GLOBAL_ALPHA,
    OSD0_MONO8_SEPARATE_ALPHA,
    
    OSD1_RGB888_GLOBAL_ALPHA,
    OSD1_RGB888_SEPARATE_ALPHA,
    OSD1_RGB565_GLOBAL_ALPHA,
    OSD1_RGB565_SEPARATE_ALPHA,
    OSD1_ARGB8888_GLOBAL_ALPHA,
    OSD1_ARGB8888_SEPARATE_ALPHA,
    OSD1_ARGB8888_PIXEL_ALPHA,
    OSD1_ARGB4444_GLOBAL_ALPHA,
    OSD1_ARGB4444_SEPARATE_ALPHA,
    OSD1_ARGB4444_PIXEL_ALPHA,
    OSD1_ARGB1555_GLOBAL_ALPHA,
    OSD1_ARGB1555_SEPARATE_ALPHA,
    OSD1_ARGB1555_PIXEL_ALPHA,
    OSD1_MONO8_GLOBAL_ALPHA,
    OSD1_MONO8_SEPARATE_ALPHA,
    
    OSD2_RGB888_GLOBAL_ALPHA,
    OSD2_RGB888_SEPARATE_ALPHA,
    OSD2_RGB565_GLOBAL_ALPHA,
    OSD2_RGB565_SEPARATE_ALPHA,
    OSD2_ARGB8888_GLOBAL_ALPHA,
    OSD2_ARGB8888_SEPARATE_ALPHA,
    OSD2_ARGB8888_PIXEL_ALPHA,
    OSD2_ARGB4444_GLOBAL_ALPHA,
    OSD2_ARGB4444_SEPARATE_ALPHA,
    OSD2_ARGB4444_PIXEL_ALPHA,
    OSD2_ARGB1555_GLOBAL_ALPHA,
    OSD2_ARGB1555_SEPARATE_ALPHA,
    OSD2_ARGB1555_PIXEL_ALPHA,
    OSD2_MONO8_GLOBAL_ALPHA,
    OSD2_MONO8_SEPARATE_ALPHA,

    OSD0_OUTPUT_WINDOW_MOVE,
    OSD1_OUTPUT_WINDOW_MOVE,
    OSD2_OUTPUT_WINDOW_MOVE,

    OSD0_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD0_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD0_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD0_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD0_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD0_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,
    
    OSD1_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD1_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD1_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD1_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD1_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD1_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,
    
    OSD2_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD2_ARGB8888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD2_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD2_ARGB8888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD2_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD2_ARGB8888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,

    OSD0_RGB888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD0_RGB888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD0_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD0_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD0_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD0_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,
    
    OSD1_RGB888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD1_RGB888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD1_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD1_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD1_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD1_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,
    
    OSD2_RGB888_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD2_RGB888_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD2_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD2_RGB888_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD2_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD2_RGB888_DMA_CTL_MAP_TWOBYTESWAP_REV_B,

    OSD0_RGB565_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD0_RGB565_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD0_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD0_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD0_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD0_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_B,    
    OSD0_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD0_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD0_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD0_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD0_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD0_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_B,
    OSD0_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD0_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD0_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD0_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD0_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD0_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_B,

    OSD1_RGB565_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD1_RGB565_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD1_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD1_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD1_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD1_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_B,    
    OSD1_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD1_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD1_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD1_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD1_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD1_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_B,    
    OSD1_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD1_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD1_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD1_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD1_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD1_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_B,

    OSD2_RGB565_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD2_RGB565_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD2_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD2_RGB565_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD2_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD2_RGB565_DMA_CTL_MAP_TWOBYTESWAP_REV_B,    
    OSD2_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD2_ARGB4444_DMA_CTL_MAP_ORIGINAL_REV_B,
    OSD2_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_R,    
    OSD2_ARGB4444_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD2_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_R,    
    OSD2_ARGB4444_DMA_CTL_MAP_TWOBYTESWAP_REV_B,    
    OSD2_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_R,
    OSD2_ARGB1555_DMA_CTL_MAP_ORIGINAL_REV_B,   
    OSD2_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_R,
    OSD2_ARGB1555_DMA_CTL_MAP_ENDIANSWAP_REV_B,
    OSD2_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_R,
    OSD2_ARGB1555_DMA_CTL_MAP_TWOBYTESWAP_REV_B,

    OSD0_ARGB8888_SIZE,
    OSD0_RGB888_SIZE,
    OSD0_RGB565_SIZE,
    OSD0_ARGB4444_SIZE,
    OSD0_ARGB1555_SIZE,
    OSD0_MONO8_SIZE,

    OSD1_ARGB8888_SIZE,
    OSD1_RGB888_SIZE,
    OSD1_RGB565_SIZE,
    OSD1_ARGB4444_SIZE,
    OSD1_ARGB1555_SIZE,
    OSD1_MONO8_SIZE,

    OSD2_ARGB8888_SIZE,
    OSD2_RGB888_SIZE,
    OSD2_RGB565_SIZE,
    OSD2_ARGB4444_SIZE,
    OSD2_ARGB1555_SIZE,
    OSD2_MONO8_SIZE,
    
    OSD_ARGB8888_ALPHA_TRAVERSAL,
    OSD_RGB888_ALPHA_TRAVERSAL,
    DMA_SRAM,
    //end
    
//detailed
    REG_DEFAULT_VALUE,
    REG_WRITE_READ_VALUE,
    BACKGROUND_COMPONENT,
    LAYERS_ADDRESS_SWITCH,
    LAYER0_RESET,
    OUTPUT_1280720_50FPS,
    OUTPUT_1280720_60FPS,
    OUTPUT_1280720_30FPS,
    OUTPUT_1280720_25FPS,
    VIDEO_LAYER_ALPHA_TRAVERSAL,
    DISPLAY_MIXER,
    DISPLAY_MIXER_FORMAT,
    VIDEO_LAYER_REGRESSION,
    
    //to co-ordinate isp ds test
    LAYER1_420_DS_OUT0_1080_YUV420_UVSWAP,
    LAYER1_420_DS_OUT0_720_YUV422,
    LAYER_420_DS_OUT_ALL_YUV420,
    LAYER_420_DS_OUT_ALL_DS0_YUV420,
    LAYER_420_DS_OUT_ALL_DS1_YUV420,
    LAYER_420_DS_OUT_ALL_DS2_YUV420,
    LAYER_420_DS0_DS2_OUT_OSD1_YUV420,
    LAYER1_420_DS_OUT0_576_YUV420,
    LAYER1_420_DS_OUT0_VGA_YUV420,
    LAYER1_420_DS_OUT0_320x240_YUV420,
    LAYER1_420_DS_OUT0_320x240_YUV422,
    LAYER1_420_DS_OUT0_128x64_YUV420,
    LAYER1_420_DS_OUT1_1080_YUV420_UVSWAP,    
    LAYER1_420_DS_OUT1_720_YUV422,
    LAYER1_420_DS_OUT1_576_YUV420,
    LAYER1_420_DS_OUT1_VGA_YUV420,
    LAYER1_420_DS_OUT1_320x240_YUV420,
    LAYER1_420_DS_OUT1_320x240_YUV422,
    LAYER1_420_DS_OUT1_128x64_YUV420,
    LAYER1_420_DS_OUT2_1080_YUV420_UVSWAP,    
    LAYER1_420_DS_OUT2_1080_YUV420,
    LAYER1_420_DS_OUT2_720_YUV422,
    LAYER1_420_DS_OUT2_576_YUV420,
    LAYER1_420_DS_OUT2_VGA_YUV420,
    LAYER1_420_DS_OUT2_320x240_YUV420,
    LAYER1_420_DS_OUT2_320x240_YUV422,
    LAYER1_420_DS_OUT2_128x64_YUV420,
    OSDLAYER0_420_DS_OUT2_1080_RGB,
    OSDLAYER0_420_DS_OUT2_720_RGB,
    OSDLAYER0_420_DS_OUT2_576_RGB,
    OSDLAYER0_420_DS_OUT2_VGA_RGB,
    OSDLAYER0_420_DS_OUT2_320x240_RGB,
    OSDLAYER0_420_DS_OUT2_128x64_RGB,
    OSD0_DS_OUT2_RGB32,
    TEST_2D_LAYER0_420,
    VO_CASE_LAYER_TD_MIXER_TEST,
    VO_CASE_LAYER_TD_ROTATION_TEST,
    VO_CASE_LAYER_TD_ROTATION_TEST_422,
    VO_CASE_LAYER_TD_ROTATION_MIXER_TEST,
    VO_CASE_LAYER_TD_MIXER_VOUT_COMPARE_TEST,
    VO_CASE_LAYER_TD_MIXER_SCALER_2D,
    VO_CASE_LAYER_TD_TOTATION_REGRESS_2D,
    VO_CASE_LAYER0_MFBD,
    VO_CASE_LAYER0_DS0_1080x720_MFBD,
    VO_CASE_LAYER0_LINE_DRAW,
    VO_CASE_MIXER_WRITE_BACK,
    LAYER_420_DS_FRAME_DRAW_YUV420,
    LAYER0_420_1080x1920_YUV420_DSI,
    LAYER0_420_BT1120,
    VO_CASE_LAYER0_LAYER1,
    LAYER0_420_IRS238C,
    VO_DSI_LAYER0_420_IRS238C,
    LAYER0_420_TOF_VGA,
    VO_DSI_LAYER0_420_TOF_VGA,
	VO_CASE_LAYER0_420_F23S_IRS238C,
	VO_CASE_LAYER0_420_1280x720_1920x1080,
	VO_DSI_MIPI_BRINGUP,
    VO_DSI_MIPI_ALLDS_BRINGUP,
    VO_DSI_MIPI_ALLDS_MFBD_BRINGUP,
    VO_DSI_MIPI_DS0_BRINGUP,
    VO_DSI_MIPI_DS1_BRINGUP,
    VO_DSI_MIPI_DS2_BRINGUP,
    VO_BT1120_HDMI_BRINGUP,
    VO_TEST_CASE_MAX,
}VO_TEST_CASE_E;

typedef enum _ISP_TABLE_NAME{
    RGB_GAMMA,
    YUV_GAMMA,
    WDR_L3,
    WDR_M3,
    WDR_S3,
    WDR_L2,
    WDR_S2,
    TABLE_MAX,
}ISP_TABLE;

//isp
#define ISP_BUF_MAIN_Y              0x05000000//0x20000000
#define ISP_BUF_MAIN_UV             0x051fa400//0x20280000
#define ISP_BUF_MAIN_Y_STRIDE       0x780//0x800
#define ISP_BUF_MAIN_UV_STRIDE      0x780//0x800
#define ISP_BUF_DS2_R_STRIDE_LARGE  0x1E00

#define ISP_4K_BUF_DS0_Y            0x05000000//0x20400000
#define ISP_4K_BUF_DS0_UV           0x051fa400//0x20680000
#define ISP_4K_BUF_DS0_Y_STRIDE     0x780//0x800
#define ISP_4K_BUF_DS0_UV_STRIDE    0x780//0x800

#define ISP_BUF_DS0_Y               0x05400000//0x02600000//0x20600000
#define ISP_BUF_DS0_UV              0x054E1000//0x02880000//0x20880000
#define ISP_BUF_DS0_Y_STRIDE        0x500//0x800
#define ISP_BUF_DS0_UV_STRIDE       0x500//0x800

#define ISP_BUF_DS1_Y               0x05600000//0x02A00000//0x20A00000
#define ISP_BUF_DS1_UV              0x05612C00//0x02C80000 //0x20C80000
#define ISP_BUF_DS1_Y_STRIDE        0x140//0x800
#define ISP_BUF_DS1_UV_STRIDE       0x140//0x800

#define ISP_BUF_DS2_R          		0x05700000//0x22000000
#define ISP_BUF_DS2_G          		0x05712C00//0x22400000
#define ISP_BUF_DS2_B          		0x05725800//0x22800000

#define ISP_BUF_DS2_ARGB_R          0x05700000//0x22000000
#define ISP_BUF_DS2_ARGB_G          0x05700140//0x05712C00//0x22400000
#define ISP_BUF_DS2_ARGB_B          0x05700280// //0x05725800//0x22800000

#define ISP_BUF_DS2_R_STRIDE        (0x140)//0x800
#define ISP_BUF_DS2_G_STRIDE        (0x140)//0x800
#define ISP_BUF_DS2_B_STRIDE        (0x140)//0x800

#define ISP_BUF_3DNR_Y              0x06000000  //+0X2F7600 1920x1080  12bit
#define ISP_BUF_3DNR_UV             0x06300000  //+0x1fa400 1920x1080  8bit
#define ISP_BUF_3DNR_Y_STRIDE       0xb40       //0xc00
#define ISP_BUF_3DNR_UV_STRIDE      0x780       //0x800

#define ISP_BUF_LDC_Y               0x06500000
#define ISP_BUF_LDC_UV              0x06900000//0x066FA400 
#define ISP_BUF_LDC_Y_STRIDE        0x800 //0x780
#define ISP_BUF_LDC_UV_STRIDE       0x800 //0x780

#define ISP_4K_BUF_3DNR_Y           0x06000000  //4096x2160  12bit
#define ISP_4K_BUF_3DNR_UV          0x06ca8000  //4096x2160  12bit
#define ISP_4K_BUF_3DNR_Y_STRIDE    0x1800
#define ISP_4K_BUF_3DNR_UV_STRIDE   0x1000

#define ISP_BUF_MFBC_Y              0x07000000 //0x31000000
#define ISP_BUF_MFBC_Y_STRIDE       0x2000
#define ISP_BUF_MFBC_Y_BLEN         0x7
#define ISP_BUF_MFBC_Y_HEAD         0x07c00000
#define ISP_BUF_MFBC_Y_HEAD_STRIDE  0x100
#define ISP_BUF_MFBC_Y_HEAD_BLEN    0x3

#define ISP_BUF_MFBC_UV             0x07400000 //0x31400000
#define ISP_BUF_MFBC_UV_STRIDE      0x2000
#define ISP_BUF_MFBC_UV_BLEN        0x7
#define ISP_BUF_MFBC_UV_HEAD        0x07d00000
#define ISP_BUF_MFBC_UV_HEAD_STRIDE 0x100
#define ISP_BUF_MFBC_UV_HEAD_BLEN   0x3

#define ISP_BUF_MFBC_YL             0x07800000 //0x31C00000
#define ISP_BUF_MFBC_YL_STRIDE      0x1000
#define ISP_BUF_MFBC_YL_BLEN        0x7
#define ISP_BUF_MFBC_YL_HEAD        0x07e00000
#define ISP_BUF_MFBC_YL_HEAD_STRIDE 0x100
#define ISP_BUF_MFBC_YL_HEAD_BLEN   0x3

#define ISP_BUF_MFBD_Y              0x07000000
#define ISP_BUF_MFBD_Y_STRIDE       0x2000
#define ISP_BUF_MFBD_Y_HEAD         0x07c00000
#define ISP_BUF_MFBD_Y_HEAD_STRIDE  0x100

#define ISP_BUF_MFBD_UV             0x07400000
#define ISP_BUF_MFBD_UV_STRIDE      0x2000
#define ISP_BUF_MFBD_UV_HEAD        0x07d00000
#define ISP_BUF_MFBD_UV_HEAD_STRIDE 0x100
#define ISP_BUF_MFBD_UV_HEAD_BLEN   0x3

#define ISP_BUF_MFBD_YL             0x07800000
#define ISP_BUF_MFBD_YL_STRIDE      0x1000
#define ISP_BUF_MFBD_YL_HEAD        0x07e00000
#define ISP_BUF_MFBD_YL_HEAD_STRIDE 0x100

#define ISP_OSD_RGB_ADDR            0x04000000
#define ISP_OSD_RGB_STRIDE          1920  //7680
#define ISP_OSD_ALPHA_ADDR          0x04000000
#define ISP_OSD_ALPHA_STRIDE        640 //640>>3
//isp tof
#define TOF_BUF_DEPTH               0x05900000//0x24000000 //0x20000000
#define TOF_BUF_DEPTH_STRIDE        0x100 //0x800
#define TOF_BUF_GRAY                0x05a00000//0x20200000
#define TOF_BUF_GRAY_STRIDE         0x100 //0x800

//
#define ISP_TPG_W_Y_1920_BUF 	    0x01000000//0x30000000
#define ISP_TPG_W_UV_1920_BUF	    0x0121c000//0x30000000
#define ISP_TPG_W_Y_1920_STRIDE	    0xb40//0x1000
#define ISP_TPG_W_UV_1920_STRIDE    0xb40//0x1000
#define ISP_TPG_R_Y_1920_BUF	    0x01000000//0x30000000
#define ISP_TPG_R_Y_1920_STRIDE	    0xb40//0x1000
//
#define ISP_TPG_W_Y_320_BUF 	    0x01000000//0x30000000
#define ISP_TPG_W_UV_320_BUF	    0x0121c000//0x30000000
#define ISP_TPG_W_Y_320_STRIDE	    0x1e0//0x1000
#define ISP_TPG_W_UV_320_STRIDE     0x1e0//0x1000
#define ISP_TPG_R_Y_320_BUF	 	    0x01000000//0x30000000
#define ISP_TPG_R_Y_320_STRIDE	    0x1e0//0x1000
//
#define MFBC_Y_DATA_WR_ADDR0        0x02000000
#define MFBC_Y_DATA_WR_ADDR1        0x02000000

#define MFBC_Y_HEAD_WR_ADDR0        0x03000000
#define MFBC_Y_HEAD_WR_ADDR1        0x03000000

#define MFBC_UV_DATA_WR_ADDR0       0x02280000
#define MFBC_UV_DATA_WR_ADDR1       0x02280000

#define MFBC_UV_HEAD_WR_ADDR0       0x03280000
#define MFBC_UV_HEAD_WR_ADDR1       0x03280000
#define MFBC_DATA_STRIDE       	    1920 //2048

#define MFBC_INPUT_HOR              1920
#define MFBC_INPUT_VER              1080

typedef struct _IMAGE_SIZE{
	unsigned int Width;
	unsigned int Height;	
}IMAGE_SIZE;

typedef struct _CRITICAL_MODULE_EN
{
	ISP_PIPE_MODE_E 	enIspMode;
    ISP_PIPE_DOWN_STREAM_E down_stream;
    ISP_PIPE_WDR_MODE_E wdr_mode;
    unsigned int main_en;
    unsigned int remap_main_en;//
    unsigned int ds0_en;
    unsigned int remap0_en;//
    unsigned int ds0_osd0_en;
    unsigned int ds0_osd1_en;
    unsigned int ds0_osd2_en;
    unsigned int ds1_en;
    unsigned int remap1_en;//
    unsigned int ds1_osd0_en;
    unsigned int ds1_osd1_en;
    unsigned int ds1_osd2_en;
    unsigned int ds2_en;
    unsigned int ds2_osd0_en;
    unsigned int ds2_osd1_en;
    unsigned int ds2_osd2_en;
    unsigned int soc_mfbcd_en;
    unsigned int isp_tpg_en;
    unsigned int vi_tpg_en;
    //
    unsigned int blc_en;
    //
    unsigned int lsc_en;
    //
    unsigned int otc_en;
    //
    unsigned int rgbir_en;
    unsigned int rgbir_fusion_en;
    unsigned int rgbir_out_infrared_en;
    //
    unsigned int ae_en;
    unsigned int ae_auto_adj;
    //
    unsigned int awb_en;
    unsigned int awb_auto_adj;
    //
    unsigned int nr2d_en;
    unsigned int nr2d_auto_adj;
    //
    unsigned int nr3d_en;
    unsigned int nr3d_mfbcd_en;
    //
    unsigned int ldc_en;
}CRITICAL_MODULE_EN;

#define ISP_PRINTF_FUNC  	    printf
#define ISP_DEBUG_OPEN	        0
#define ISP_WRAP_DEBUG_OPEN	    0
#define ISP_CORE_DEBUG_OPEN	    0
#define ISP_MFBC_DEBUG_OPEN	    0
#define ISP_MFBD_DEBUG_OPEN	    0
#define ISP_DS_DEBUG_OPEN 	    0
#define ISP_REMAP_DEBUG_OPEN    0

#define ISP_MAX_DEV_NUM         4
#define ISP_DS_CH_NUM           3
#define ISP_DS_CH_OSD_NUM       3

#define ISP_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            ISP_PRINTF_FUNC("ISP Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#define TOF_DEBUG_OPEN 0
#define TOF_WRAP_DEBUG_OPEN 0
#define TOF_CORE_DEBUG_OPEN 0
#define TOF_PRINTF_FUNC  printf
#define TOF_CHECK_POINTER(ptr)\
		do {\
			if (NULL == ptr)\
			{\
				TOF_PRINTF_FUNC("TOF Module: Null Pointer!\n");\
				return -1;\
			}\
		}while(0);

#define MFBC_DEBUG_OPEN 0
#define MFBC_WRAP_DEBUG_OPEN 0
#define MFBC_CORE_DEBUG_OPEN 0

#define MFBC_PRINTF_FUNC  printf

#define MFBC_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            MFBC_PRINTF_FUNC("MFBC Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#define TD_PRINTF_FUNC  	    printf
#define TD_DEBUG_OPEN 		    0
#define TD_WRAP_DEBUG_OPEN 		0
#define TD_CORE_DEBUG_OPEN 		0

#define TD_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            TD_PRINTF_FUNC("TD Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#define VI_DEBUG_OPEN 0
#define VI_WRAP_DEBUG_OPEN 0
#define VI_PIPE_DEBUG_OPEN 0
#define VI_PRINTF_FUNC  printf

#define VI_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            VI_PRINTF_FUNC("VI Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#define VI_CHECK_DEV(dev)\
	do {\
		if (((dev) < 0) || ((dev) >= VI_MAX_DEV_NUM))\
		{\
			VI_PRINTF_FUNC("VI Module: Err Device Index!\n");\
			return -1;\
		}\
	}while(0);

#define VI_CHECK_PIPE(pipe)\
	do {\
		if (((pipe) < VI_MIPI_CSI00_PIPE_ID) || ((pipe) >= VI_MAX_PIPE_NUM))\
		{\
			VI_PRINTF_FUNC("VI Module: Err Vin Pipe Index!\n");\
			return -1;\
		}\
	}while(0);


#define VO_PRINTF_FUNC  	printf
#define VO_DEBUG_OPEN 		1
#define VO_CORE_DEBUG_OPEN 	0
#define VO_REMAP_DEBUG_OPEN 0
#define VO_TABLE_DEBUG_OPEN 0

#define VO_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            VO_PRINTF_FUNC("VO Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#define BT1120_DEBUG_OPEN   1
#define BT1120_PRINTF_FUNC  printf

#define BT1120_CHECK_POINTER(ptr)\
    do {\
        if (NULL == ptr)\
        {\
            BT1120_PRINTF_FUNC("BT1120 Module: Null Pointer!\n");\
            return -1;\
        }\
    }while(0);

#endif /* _ISP_COM_DEF_H_ */
