/* Copyright (C) 2019 Cadence Design Systems.  All rights reserved           */
/* THIS FILE IS AUTOMATICALLY GENERATED BY CADENCE BLUEPRINT, DO NOT EDIT    */
/*                                                                           */


#ifndef ____REG_EMAC_REGS_MACRO_H__
#define ____REG_EMAC_REGS_MACRO_H__


/* macros for BlueprintGlobalNameSpace::network_control */
#ifndef __EMAC_REGS__NETWORK_CONTROL_MACRO__
#define __EMAC_REGS__NETWORK_CONTROL_MACRO__

/* macros for field loopback */
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SHIFT                                      0
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WIDTH                                      1
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MASK                             0x00000001U
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__RESET                                      0
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WRITE(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field loopback_local */
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SHIFT                                1
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MASK                       0x00000002U
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field enable_receive */
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SHIFT                                2
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MASK                       0x00000004U
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field enable_transmit */
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SHIFT                               3
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WIDTH                               1
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MASK                      0x00000008U
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__RESET                               0
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field man_port_en */
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SHIFT                                   4
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WIDTH                                   1
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MASK                          0x00000010U
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__RESET                                   0
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field clear_all_stats_regs */
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SHIFT                          5
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WIDTH                          1
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MASK                 0x00000020U
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__RESET                          0
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field inc_all_stats_regs */
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SHIFT                            6
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WIDTH                            1
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MASK                   0x00000040U
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__RESET                            0
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field stats_write_en */
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SHIFT                                7
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MASK                       0x00000080U
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field back_pressure */
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SHIFT                                 8
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WIDTH                                 1
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MASK                        0x00000100U
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__RESET                                 0
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field transmit_start */
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__SHIFT                                9
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__MASK                       0x00000200U
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_START__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field transmit_halt */
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__SHIFT                                10
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__WIDTH                                 1
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__MASK                        0x00000400U
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__RESET                                 0
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_HALT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field tx_pause_frame_req */
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SHIFT                           11
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WIDTH                            1
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MASK                   0x00000800U
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__RESET                            0
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field tx_pause_frame_zero */
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SHIFT                          12
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WIDTH                           1
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MASK                  0x00001000U
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__RESET                           0
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field stats_take_snap */
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SHIFT                              13
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WIDTH                               1
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MASK                      0x00002000U
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__RESET                               0
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field stats_read_snap */
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SHIFT                              14
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WIDTH                               1
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MASK                      0x00004000U
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__RESET                               0
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field store_rx_ts */
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SHIFT                                  15
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WIDTH                                   1
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MASK                          0x00008000U
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__RESET                                   0
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field pfc_enable */
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SHIFT                                   16
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WIDTH                                    1
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MASK                           0x00010000U
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__RESET                                    0
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field transmit_pfc_priority_based_pause_frame */
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SHIFT      17
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WIDTH       1
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MASK \
                    0x00020000U
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__RESET       0
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field flush_rx_pkt_pclk */
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SHIFT                            18
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WIDTH                             1
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MASK                    0x00040000U
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__RESET                             0
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field tx_lpi_en */
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SHIFT                                    19
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WIDTH                                     1
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MASK                            0x00080000U
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__RESET                                     0
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field ptp_unicast_ena */
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SHIFT                              20
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WIDTH                               1
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MASK                      0x00100000U
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__RESET                               0
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field alt_sgmii_mode */
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SHIFT                               21
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MASK                       0x00200000U
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field store_udp_offset */
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SHIFT                             22
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WIDTH                              1
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MASK                     0x00400000U
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__RESET                              0
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00400000U)
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((uint32_t)(src) <<\
                    22) & 0x00400000U)
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00400000U)))
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field ext_tsu_port_enable */
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SHIFT                          23
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WIDTH                           1
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MASK                  0x00800000U
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__RESET                           0
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field one_step_sync_mode */
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SHIFT                           24
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WIDTH                            1
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MASK                   0x01000000U
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__RESET                            0
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field pfc_ctrl */
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SHIFT                                     25
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WIDTH                                      1
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MASK                             0x02000000U
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__RESET                                      0
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field ext_rxq_sel_en */
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SHIFT                               26
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WIDTH                                1
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MASK                       0x04000000U
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__RESET                                0
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field oss_correction_field */
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SHIFT                         27
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WIDTH                          1
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MASK                 0x08000000U
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__RESET                          0
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field sel_mii_on_rgmii */
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SHIFT                             28
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WIDTH                              1
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MASK                     0x10000000U
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__RESET                              0
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field two_pt_five_gig */
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SHIFT                              29
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WIDTH                               1
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MASK                      0x20000000U
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__RESET                               0
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field ifg_eats_qav_credit */
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SHIFT                          30
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WIDTH                           1
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MASK                  0x40000000U
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__RESET                           0
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field enable_hs_mac */
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__SHIFT                                31
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__WIDTH                                 1
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__MASK                        0x80000000U
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__RESET                                 0
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__NETWORK_CONTROL__ENABLE_HS_MAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__NETWORK_CONTROL__TYPE                                          uint32_t
#define EMAC_REGS__NETWORK_CONTROL__READ                                       0xfff9c19fU
#define EMAC_REGS__NETWORK_CONTROL__WRITE                                      0xfff9c19fU

#endif /* __NETWORK_CONTROL_MACRO__ */


/* macros for network_control */
#define EMAC_REGS__INST_NETWORK_CONTROL__NUM                                             1

/* macros for BlueprintGlobalNameSpace::network_config */
#ifndef __EMAC_REGS__NETWORK_CONFIG_MACRO__
#define __EMAC_REGS__NETWORK_CONFIG_MACRO__

/* macros for field speed */
#define EMAC_REGS__NETWORK_CONFIG__SPEED__SHIFT                                          0
#define EMAC_REGS__NETWORK_CONFIG__SPEED__WIDTH                                          1
#define EMAC_REGS__NETWORK_CONFIG__SPEED__MASK                                 0x00000001U
#define EMAC_REGS__NETWORK_CONFIG__SPEED__RESET                                          0
#define EMAC_REGS__NETWORK_CONFIG__SPEED__READ(src)        ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__NETWORK_CONFIG__SPEED__WRITE(src)       ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__NETWORK_CONFIG__SPEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__NETWORK_CONFIG__SPEED__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__NETWORK_CONFIG__SPEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__NETWORK_CONFIG__SPEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field full_duplex */
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SHIFT                                    1
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WIDTH                                    1
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MASK                           0x00000002U
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__RESET                                    0
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field discard_non_vlan_frames */
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SHIFT                        2
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WIDTH                        1
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MASK               0x00000004U
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__RESET                        0
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field jumbo_frames */
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SHIFT                                   3
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WIDTH                                   1
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MASK                          0x00000008U
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__RESET                                   0
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field copy_all_frames */
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SHIFT                                4
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WIDTH                                1
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MASK                       0x00000010U
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__RESET                                0
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field no_broadcast */
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SHIFT                                   5
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WIDTH                                   1
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MASK                          0x00000020U
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__RESET                                   0
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field multicast_hash_enable */
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SHIFT                          6
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WIDTH                          1
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MASK                 0x00000040U
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__RESET                          0
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field unicast_hash_enable */
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SHIFT                            7
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WIDTH                            1
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MASK                   0x00000080U
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__RESET                            0
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field receive_1536_byte_frames */
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SHIFT                       8
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WIDTH                       1
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MASK              0x00000100U
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__RESET                       0
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field external_address_match_enable */
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SHIFT                  9
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WIDTH                  1
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MASK         0x00000200U
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__RESET                  0
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field gigabit_mode_enable */
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SHIFT                           10
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WIDTH                            1
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MASK                   0x00000400U
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__RESET                            0
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field pcs_select */
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SHIFT                                    11
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WIDTH                                     1
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MASK                            0x00000800U
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__RESET                                     0
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field retry_test */
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SHIFT                                    12
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WIDTH                                     1
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MASK                            0x00001000U
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__RESET                                     0
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field pause_enable */
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SHIFT                                  13
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WIDTH                                   1
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MASK                          0x00002000U
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__RESET                                   0
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field receive_buffer_offset */
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__SHIFT                         14
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WIDTH                          2
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MASK                 0x0000c000U
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__RESET                          0
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000c000U) >> 14)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x0000c000U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((uint32_t)(src) <<\
                    14) & 0x0000c000U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field length_field_error_frame_discard */
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SHIFT              16
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WIDTH               1
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MASK      0x00010000U
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__RESET               0
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field fcs_remove */
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SHIFT                                    17
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WIDTH                                     1
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MASK                            0x00020000U
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__RESET                                     0
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field mdc_clock_division */
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__SHIFT                            18
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WIDTH                             3
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MASK                    0x001c0000U
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__RESET                             2
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x001c0000U) >> 18)
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x001c0000U)
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x001c0000U) | (((uint32_t)(src) <<\
                    18) & 0x001c0000U)
#define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x001c0000U)))

/* macros for field data_bus_width */
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__SHIFT                                21
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WIDTH                                 2
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MASK                        0x00600000U
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__RESET                                 0
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00600000U) >> 21)
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00600000U)
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00600000U) | (((uint32_t)(src) <<\
                    21) & 0x00600000U)
#define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00600000U)))

/* macros for field disable_copy_of_pause_frames */
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SHIFT                  23
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WIDTH                   1
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MASK          0x00800000U
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__RESET                   0
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field receive_checksum_offload_enable */
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SHIFT               24
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WIDTH                1
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MASK       0x01000000U
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__RESET                0
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field en_half_duplex_rx */
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SHIFT                             25
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WIDTH                              1
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MASK                     0x02000000U
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__RESET                              0
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field ignore_rx_fcs */
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SHIFT                                 26
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WIDTH                                  1
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MASK                         0x04000000U
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__RESET                                  0
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field sgmii_mode_enable */
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SHIFT                             27
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WIDTH                              1
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MASK                     0x08000000U
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__RESET                              0
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field ipg_stretch_enable */
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SHIFT                            28
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WIDTH                             1
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MASK                    0x10000000U
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__RESET                             0
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field nsp_accept */
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__SHIFT                                    29
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__WIDTH                                     1
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__MASK                            0x20000000U
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__RESET                                     0
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__NETWORK_CONFIG__NSP_ACCEPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field ignore_ipg_rx_er */
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SHIFT                              30
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WIDTH                               1
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MASK                      0x40000000U
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__RESET                               0
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field uni_direction_enable */
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SHIFT                          31
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WIDTH                           1
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MASK                  0x80000000U
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__RESET                           0
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__NETWORK_CONFIG__TYPE                                           uint32_t
#define EMAC_REGS__NETWORK_CONFIG__READ                                        0xffffffffU
#define EMAC_REGS__NETWORK_CONFIG__WRITE                                       0xffffffffU

#endif /* __NETWORK_CONFIG_MACRO__ */


/* macros for network_config */
#define EMAC_REGS__INST_NETWORK_CONFIG__NUM                                              1

/* macros for BlueprintGlobalNameSpace::network_status */
#ifndef __EMAC_REGS__NETWORK_STATUS_MACRO__
#define __EMAC_REGS__NETWORK_STATUS_MACRO__

/* macros for field pcs_link_state */
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SHIFT                                 0
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__WIDTH                                 1
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__MASK                        0x00000001U
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__RESET                                 0
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field mdio_in */
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SHIFT                                        1
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__WIDTH                                        1
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__MASK                               0x00000002U
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__RESET                                        0
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__NETWORK_STATUS__MDIO_IN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field man_done */
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SHIFT                                       2
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__WIDTH                                       1
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__MASK                              0x00000004U
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__RESET                                       1
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__NETWORK_STATUS__MAN_DONE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field mac_full_duplex */
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SHIFT                                3
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__WIDTH                                1
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__MASK                       0x00000008U
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__RESET                                0
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field mac_pause_rx_en */
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SHIFT                                4
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__WIDTH                                1
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__MASK                       0x00000010U
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__RESET                                0
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field mac_pause_tx_en */
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SHIFT                                5
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__WIDTH                                1
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__MASK                       0x00000020U
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__RESET                                0
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field pfc_negotiate_pclk */
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SHIFT                             6
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__WIDTH                             1
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__MASK                    0x00000040U
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__RESET                             0
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field lpi_indicate_pclk */
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SHIFT                              7
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__WIDTH                              1
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__MASK                     0x00000080U
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__RESET                              0
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field axi_xaction_outstanding */
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__SHIFT                        8
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__WIDTH                        1
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__MASK               0x00000100U
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__RESET                        0
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__NETWORK_STATUS__AXI_XACTION_OUTSTANDING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field link_fault_indication */
#define EMAC_REGS__NETWORK_STATUS__LINK_FAULT_INDICATION__SHIFT                          9
#define EMAC_REGS__NETWORK_STATUS__LINK_FAULT_INDICATION__WIDTH                          2
#define EMAC_REGS__NETWORK_STATUS__LINK_FAULT_INDICATION__MASK                 0x00000600U
#define EMAC_REGS__NETWORK_STATUS__LINK_FAULT_INDICATION__RESET                          0
#define EMAC_REGS__NETWORK_STATUS__LINK_FAULT_INDICATION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000600U) >> 9)

/* macros for field reserved_31_11 */
#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_11__SHIFT                                11
#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_11__WIDTH                                21
#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_11__MASK                        0xfffff800U
#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_11__RESET                                 0
#define EMAC_REGS__NETWORK_STATUS__RESERVED_31_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff800U) >> 11)
#define EMAC_REGS__NETWORK_STATUS__TYPE                                           uint32_t
#define EMAC_REGS__NETWORK_STATUS__READ                                        0xffffffffU

#endif /* __NETWORK_STATUS_MACRO__ */


/* macros for network_status */
#define EMAC_REGS__INST_NETWORK_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::user_io_register */
#ifndef __EMAC_REGS__USER_IO_REGISTER_MACRO__
#define __EMAC_REGS__USER_IO_REGISTER_MACRO__

/* macros for field user_programmable_outputs */
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__SHIFT                    0
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WIDTH                   16
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MASK           0x0000ffffU
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__RESET                    0
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field user_programmable_inputs */
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__SHIFT                    16
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__WIDTH                    16
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__MASK            0xffff0000U
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__RESET                     0
#define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__USER_IO_REGISTER__TYPE                                         uint32_t
#define EMAC_REGS__USER_IO_REGISTER__READ                                      0xffffffffU
#define EMAC_REGS__USER_IO_REGISTER__WRITE                                     0xffffffffU

#endif /* __USER_IO_REGISTER_MACRO__ */


/* macros for user_io_register */
#define EMAC_REGS__INST_USER_IO_REGISTER__NUM                                            1

/* macros for BlueprintGlobalNameSpace::dma_config */
#ifndef __EMAC_REGS__DMA_CONFIG_MACRO__
#define __EMAC_REGS__DMA_CONFIG_MACRO__

/* macros for field amba_burst_length */
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__SHIFT                                  0
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WIDTH                                  5
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MASK                         0x0000001fU
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__RESET                                  4
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000001fU)
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000001fU)
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000001fU) | ((uint32_t)(src) &\
                    0x0000001fU)
#define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000001fU)))

/* macros for field hdr_data_splitting_en */
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SHIFT                              5
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WIDTH                              1
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MASK                     0x00000020U
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__RESET                            0b0
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field endian_swap_management */
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SHIFT                             6
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WIDTH                             1
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MASK                    0x00000040U
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__RESET                             0
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field endian_swap_packet */
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SHIFT                                 7
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WIDTH                                 1
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MASK                        0x00000080U
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__RESET                                 0
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field rx_pbuf_size */
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__SHIFT                                       8
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WIDTH                                       2
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MASK                              0x00000300U
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__RESET                                       3
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000300U) >> 8)
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000300U)
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((uint32_t)(src) <<\
                    8) & 0x00000300U)
#define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field tx_pbuf_size */
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SHIFT                                      10
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WIDTH                                       1
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MASK                              0x00000400U
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__RESET                                       1
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field tx_pbuf_tcp_en */
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SHIFT                                    11
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WIDTH                                     1
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MASK                            0x00000800U
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__RESET                                     0
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field infinite_last_dbuf_size_en */
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SHIFT                        12
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WIDTH                         1
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MASK                0x00001000U
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__RESET                         0
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field crc_error_report */
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SHIFT                                  13
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WIDTH                                   1
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MASK                          0x00002000U
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__RESET                                   0
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field reserved_15_14 */
#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__SHIFT                                    14
#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__WIDTH                                     2
#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__MASK                            0x0000c000U
#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__RESET                                     0
#define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000c000U) >> 14)

/* macros for field rx_buf_size */
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__SHIFT                                       16
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WIDTH                                        8
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MASK                               0x00ff0000U
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__RESET                                        2
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field force_discard_on_err */
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SHIFT                              24
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WIDTH                               1
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MASK                      0x01000000U
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__RESET                               0
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field force_max_amba_burst_rx */
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SHIFT                           25
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WIDTH                            1
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MASK                   0x02000000U
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__RESET                            0
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field force_max_amba_burst_tx */
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SHIFT                           26
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WIDTH                            1
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MASK                   0x04000000U
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__RESET                            0
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field reserved_27 */
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__SHIFT                                       27
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__WIDTH                                        1
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__MASK                               0x08000000U
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__RESET                                        0
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__DMA_CONFIG__RESERVED_27__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field rx_bd_extended_mode_en */
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SHIFT                            28
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WIDTH                             1
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MASK                    0x10000000U
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__RESET                             0
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field tx_bd_extended_mode_en */
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SHIFT                            29
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WIDTH                             1
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MASK                    0x20000000U
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__RESET                             0
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field dma_addr_bus_width_1 */
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SHIFT                              30
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WIDTH                               1
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MASK                      0x40000000U
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__RESET                               0
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field send_bcast_to_all_qs */
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__SHIFT                              31
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__WIDTH                               1
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__MASK                      0x80000000U
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__RESET                               0
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__DMA_CONFIG__SEND_BCAST_TO_ALL_QS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__DMA_CONFIG__TYPE                                               uint32_t
#define EMAC_REGS__DMA_CONFIG__READ                                            0xffffffffU
#define EMAC_REGS__DMA_CONFIG__WRITE                                           0xffffffffU

#endif /* __DMA_CONFIG_MACRO__ */


/* macros for dma_config */
#define EMAC_REGS__INST_DMA_CONFIG__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::transmit_status */
#ifndef __EMAC_REGS__TRANSMIT_STATUS_MACRO__
#define __EMAC_REGS__TRANSMIT_STATUS_MACRO__

/* macros for field used_bit_read */
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__SHIFT                                 0
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WIDTH                                 1
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MASK                        0x00000001U
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__RESET                                 0
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field collision_occurred */
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__SHIFT                            1
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WIDTH                            1
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MASK                   0x00000002U
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__RESET                            0
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field retry_limit_exceeded */
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__SHIFT                          2
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WIDTH                          1
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MASK                 0x00000004U
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__RESET                          0
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field transmit_go */
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SHIFT                                   3
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__WIDTH                                   1
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__MASK                          0x00000008U
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__RESET                                   0
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field amba_error */
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__SHIFT                                    4
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WIDTH                                    1
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MASK                           0x00000010U
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__RESET                                    0
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field transmit_complete */
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__SHIFT                             5
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WIDTH                             1
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MASK                    0x00000020U
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__RESET                             0
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field transmit_under_run */
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__SHIFT                            6
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WIDTH                            1
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MASK                   0x00000040U
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__RESET                            0
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field late_collision_occurred */
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__SHIFT                       7
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WIDTH                       1
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MASK              0x00000080U
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__RESET                       0
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)

/* macros for field resp_not_ok */
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__SHIFT                                   8
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WIDTH                                   1
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MASK                          0x00000100U
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__RESET                                   0
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)

/* macros for field tx_mac_lockup_detected */
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__SHIFT                        9
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__WIDTH                        1
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__MASK               0x00000200U
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__RESET                        0
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)

/* macros for field tx_dma_lockup_detected */
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__SHIFT                       10
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__WIDTH                        1
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__MASK               0x00000400U
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__RESET                        0
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)

/* macros for field tx_frame_too_large */
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__SHIFT                           11
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__WIDTH                            1
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__MASK                   0x00000800U
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__RESET                            0
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__TRANSMIT_STATUS__TX_FRAME_TOO_LARGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)

/* macros for field tx_used_bit_read_midframe */
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__SHIFT                    12
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__WIDTH                     1
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__MASK            0x00001000U
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__RESET                     0
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__TRANSMIT_STATUS__TX_USED_BIT_READ_MIDFRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)

/* macros for field reserved_31_13 */
#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_13__SHIFT                               13
#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_13__WIDTH                               19
#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_13__MASK                       0xffffe000U
#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_13__RESET                                0
#define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_13__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffe000U) >> 13)
#define EMAC_REGS__TRANSMIT_STATUS__TYPE                                          uint32_t
#define EMAC_REGS__TRANSMIT_STATUS__READ                                       0xffffffffU
#define EMAC_REGS__TRANSMIT_STATUS__WRITE                                      0xffffffffU
#define EMAC_REGS__TRANSMIT_STATUS__WOCLR                                      0x00001ff7U

#endif /* __TRANSMIT_STATUS_MACRO__ */


/* macros for transmit_status */
#define EMAC_REGS__INST_TRANSMIT_STATUS__NUM                                             1

/* macros for BlueprintGlobalNameSpace::receive_q_ptr */
#ifndef __EMAC_REGS__RECEIVE_Q_PTR_MACRO__
#define __EMAC_REGS__RECEIVE_Q_PTR_MACRO__

/* macros for field dma_rx_dis_q */
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SHIFT                                    0
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WIDTH                                    1
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MASK                           0x00000001U
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__RESET                                  0b1
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__READ(src)  ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WRITE(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_1 */
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__SHIFT                                      1
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__WIDTH                                      1
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__MASK                             0x00000002U
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__RESET                                    0b0
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_rx_q_ptr */
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__SHIFT                                    2
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WIDTH                                   30
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MASK                           0xfffffffcU
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__RESET                                    0
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0xfffffffcU)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffffcU) | (((uint32_t)(src) <<\
                    2) & 0xfffffffcU)
#define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0xfffffffcU)))
#define EMAC_REGS__RECEIVE_Q_PTR__TYPE                                            uint32_t
#define EMAC_REGS__RECEIVE_Q_PTR__READ                                         0xffffffffU
#define EMAC_REGS__RECEIVE_Q_PTR__WRITE                                        0xffffffffU

#endif /* __RECEIVE_Q_PTR_MACRO__ */


/* macros for receive_q_ptr */
#define EMAC_REGS__INST_RECEIVE_Q_PTR__NUM                                               1

/* macros for BlueprintGlobalNameSpace::transmit_q_ptr */
#ifndef __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__
#define __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__

/* macros for field dma_tx_dis_q */
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SHIFT                                   0
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WIDTH                                   1
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MASK                          0x00000001U
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__RESET                                 0b1
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__READ(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_1 */
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__SHIFT                                     1
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__WIDTH                                     1
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__MASK                            0x00000002U
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__RESET                                   0b0
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_tx_q_ptr */
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__SHIFT                                   2
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WIDTH                                  30
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MASK                          0xfffffffcU
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__RESET                                   0
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0xfffffffcU)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffffcU) | (((uint32_t)(src) <<\
                    2) & 0xfffffffcU)
#define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0xfffffffcU)))
#define EMAC_REGS__TRANSMIT_Q_PTR__TYPE                                           uint32_t
#define EMAC_REGS__TRANSMIT_Q_PTR__READ                                        0xffffffffU
#define EMAC_REGS__TRANSMIT_Q_PTR__WRITE                                       0xffffffffU

#endif /* __TRANSMIT_Q_PTR_MACRO__ */


/* macros for transmit_q_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q_PTR__NUM                                              1

/* macros for BlueprintGlobalNameSpace::receive_status */
#ifndef __EMAC_REGS__RECEIVE_STATUS_MACRO__
#define __EMAC_REGS__RECEIVE_STATUS_MACRO__

/* macros for field buffer_not_available */
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__SHIFT                           0
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WIDTH                           1
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MASK                  0x00000001U
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__RESET                           0
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field frame_received */
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__SHIFT                                 1
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WIDTH                                 1
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MASK                        0x00000002U
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__RESET                                 0
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field receive_overrun */
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__SHIFT                                2
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WIDTH                                1
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MASK                       0x00000004U
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__RESET                                0
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field resp_not_ok */
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__SHIFT                                    3
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MASK                           0x00000008U
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__RESET                                    0
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field rx_mac_lockup_detected */
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__SHIFT                         4
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__WIDTH                         1
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__MASK                0x00000010U
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__RESET                         0
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field rx_dma_lockup_detected */
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__SHIFT                         5
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__WIDTH                         1
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__MASK                0x00000020U
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__RESET                         0
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_6__SHIFT                                  6
#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_6__WIDTH                                 26
#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_6__MASK                         0xffffffc0U
#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_6__RESET                                  0
#define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__RECEIVE_STATUS__TYPE                                           uint32_t
#define EMAC_REGS__RECEIVE_STATUS__READ                                        0xffffffffU
#define EMAC_REGS__RECEIVE_STATUS__WRITE                                       0xffffffffU
#define EMAC_REGS__RECEIVE_STATUS__WOCLR                                       0x0000003fU

#endif /* __RECEIVE_STATUS_MACRO__ */


/* macros for receive_status */
#define EMAC_REGS__INST_RECEIVE_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_status */
#ifndef __EMAC_REGS__INT_STATUS_MACRO__
#define __EMAC_REGS__INT_STATUS_MACRO__

/* macros for field management_frame_sent */
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SHIFT                              0
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WIDTH                              1
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MASK                     0x00000001U
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__RESET                            0b0
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SHIFT                                   1
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WIDTH                                   1
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MASK                          0x00000002U
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__RESET                                 0b0
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SHIFT                                   2
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WIDTH                                   1
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MASK                          0x00000004U
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__RESET                                 0b0
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field tx_used_bit_read */
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SHIFT                                   3
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WIDTH                                   1
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MASK                          0x00000008U
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__RESET                                 0b0
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field transmit_under_run */
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SHIFT                                 4
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WIDTH                                 1
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MASK                        0x00000010U
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__RESET                               0b0
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT             5
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH             1
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK    0x00000020U
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET           0b0
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__SHIFT                                         6
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__WIDTH                                         1
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__MASK                                0x00000040U
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__RESET                                       0b0
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_STATUS__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SHIFT                                  7
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WIDTH                                  1
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MASK                         0x00000080U
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__RESET                                0b0
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field usxgmii_int */
#define EMAC_REGS__INT_STATUS__USXGMII_INT__SHIFT                                        8
#define EMAC_REGS__INT_STATUS__USXGMII_INT__WIDTH                                        1
#define EMAC_REGS__INT_STATUS__USXGMII_INT__MASK                               0x00000100U
#define EMAC_REGS__INT_STATUS__USXGMII_INT__RESET                                      0b0
#define EMAC_REGS__INT_STATUS__USXGMII_INT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__INT_STATUS__USXGMII_INT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__INT_STATUS__USXGMII_INT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__INT_STATUS__USXGMII_INT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__INT_STATUS__USXGMII_INT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__INT_STATUS__USXGMII_INT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field link_change */
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__SHIFT                                        9
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__WIDTH                                        1
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__MASK                               0x00000200U
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__RESET                                      0b0
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__INT_STATUS__LINK_CHANGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field receive_overrun */
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SHIFT                                   10
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WIDTH                                    1
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MASK                           0x00000400U
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__RESET                                  0b0
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SHIFT                                       11
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WIDTH                                        1
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MASK                               0x00000800U
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__RESET                                      0b0
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_STATUS__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field pause_frame_with_non_zero_pause_quantum_received */
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SHIFT  12
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WIDTH   1
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MASK \
                    0x00001000U
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__RESET 0b0
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field pause_time_elapsed */
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SHIFT                                13
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WIDTH                                 1
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MASK                        0x00002000U
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__RESET                               0b0
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field pause_frame_transmitted */
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SHIFT                           14
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WIDTH                            1
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MASK                   0x00004000U
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__RESET                          0b0
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field external_interrupt */
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SHIFT                                15
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WIDTH                                 1
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MASK                        0x00008000U
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__RESET                               0b0
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field pcs_auto_negotiation_complete */
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SHIFT                     16
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WIDTH                      1
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MASK             0x00010000U
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__RESET                    0b0
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field pcs_link_partner_page_received */
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT                    17
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH                     1
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MASK            0x00020000U
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__RESET                   0b0
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field ptp_delay_req_frame_received */
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT                      18
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH                       1
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MASK              0x00040000U
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__RESET                     0b0
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field ptp_sync_frame_received */
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SHIFT                           19
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WIDTH                            1
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MASK                   0x00080000U
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__RESET                          0b0
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field ptp_delay_req_frame_transmitted */
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT                   20
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH                    1
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK           0x00100000U
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET                  0b0
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field ptp_sync_frame_transmitted */
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SHIFT                        21
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WIDTH                         1
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MASK                0x00200000U
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__RESET                       0b0
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field ptp_pdelay_req_frame_received */
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT                     22
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH                      1
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MASK             0x00400000U
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__RESET                    0b0
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00400000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((uint32_t)(src) <<\
                    22) & 0x00400000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00400000U)))
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field ptp_pdelay_resp_frame_received */
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT                    23
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH                     1
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MASK            0x00800000U
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__RESET                   0b0
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field ptp_pdelay_req_frame_transmitted */
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT                  24
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH                   1
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK          0x01000000U
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET                 0b0
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field ptp_pdelay_resp_frame_transmitted */
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT                 25
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH                  1
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK         0x02000000U
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET                0b0
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field tsu_seconds_register_increment */
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SHIFT                    26
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WIDTH                     1
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MASK            0x04000000U
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__RESET                   0b0
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field receive_lpi_indication_status_bit_change */
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SHIFT          27
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WIDTH           1
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MASK  0x08000000U
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__RESET         0b0
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field wol_interrupt */
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SHIFT                                     28
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WIDTH                                      1
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MASK                             0x10000000U
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__RESET                                    0b0
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field tsu_timer_comparison_interrupt */
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SHIFT                    29
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WIDTH                     1
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MASK            0x20000000U
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__RESET                   0b0
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field rx_lockup_detected */
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__SHIFT                                30
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__WIDTH                                 1
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__MASK                        0x40000000U
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__RESET                               0b0
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__INT_STATUS__RX_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field tx_lockup_detected */
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__SHIFT                                31
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__WIDTH                                 1
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__MASK                        0x80000000U
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__RESET                               0b0
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__INT_STATUS__TX_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__INT_STATUS__TYPE                                               uint32_t
#define EMAC_REGS__INT_STATUS__READ                                            0xffffffffU
#define EMAC_REGS__INT_STATUS__RCLR                                            0xffffffffU
#define EMAC_REGS__INT_STATUS__WRITE                                           0xffffffffU

#endif /* __INT_STATUS_MACRO__ */


/* macros for int_status */
#define EMAC_REGS__INST_INT_STATUS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::int_enable */
#ifndef __EMAC_REGS__INT_ENABLE_MACRO__
#define __EMAC_REGS__INT_ENABLE_MACRO__

/* macros for field enable_management_done_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT                   0
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH                   1
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MASK          0x00000001U
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__RESET                   0
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field enable_receive_complete_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT                  1
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH                  1
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK         0x00000002U
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET                  0
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field enable_receive_used_bit_read_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT             2
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH             1
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK    0x00000004U
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET             0
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field enable_transmit_used_bit_read_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT            3
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH            1
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK   0x00000008U
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET            0
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field enable_transmit_buffer_under_run_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT         4
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH         1
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \
                    0x00000010U
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET         0
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
                    5
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
                    0x00000020U
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
                    6
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
                    0x00000040U
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field enable_transmit_complete_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT                 7
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH                 1
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK        0x00000080U
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET                 0
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field enable_usxgmii_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__SHIFT                           8
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__WIDTH                           1
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__MASK                  0x00000100U
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__RESET                           0
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__INT_ENABLE__ENABLE_USXGMII_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field enable_link_change_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SHIFT                       9
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WIDTH                       1
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MASK              0x00000200U
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__RESET                       0
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field enable_receive_overrun_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT                  10
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH                   1
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MASK          0x00000400U
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__RESET                   0
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field enable_resp_not_ok_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT                      11
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH                       1
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK              0x00000800U
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET                       0
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field enable_pause_frame_with_non_zero_pause_quantum_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \
                    12
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \
                    0x00001000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field enable_pause_time_zero_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT                  13
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH                   1
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK          0x00002000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET                   0
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field enable_pause_frame_transmitted_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT          14
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH           1
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK  0x00004000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET           0
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field enable_external_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SHIFT                         15
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WIDTH                          1
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MASK                 0x00008000U
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__RESET                          0
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field enable_pcs_auto_negotiation_complete_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT    16
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH     1
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \
                    0x00010000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET     0
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field enable_pcs_link_partner_page_received */
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT             17
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH              1
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK     0x00020000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET              0
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field enable_ptp_delay_req_frame_received */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT               18
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH                1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK       0x00040000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET                0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field enable_ptp_sync_frame_received */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT                    19
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH                     1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MASK            0x00080000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__RESET                     0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field enable_ptp_delay_req_frame_transmitted */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT            20
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH             1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK    0x00100000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET             0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field enable_ptp_sync_frame_transmitted */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT                 21
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH                  1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK         0x00200000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET                  0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field enable_ptp_pdelay_req_frame_received */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT              22
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH               1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK      0x00400000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET               0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00400000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((uint32_t)(src) <<\
                    22) & 0x00400000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00400000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field enable_ptp_pdelay_resp_frame_received */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT             23
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH              1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK     0x00800000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET              0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field enable_ptp_pdelay_req_frame_transmitted */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT           24
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH            1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK   0x01000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET            0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field enable_ptp_pdelay_resp_frame_transmitted */
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT          25
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH           1
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK  0x02000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET           0
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field enable_tsu_seconds_register_increment */
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT             26
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH              1
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK     0x04000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET              0
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field enable_rx_lpi_indication_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT                27
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH                 1
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MASK        0x08000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__RESET                 0
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field enable_wol_event_received_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT               28
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK       0x10000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET                0
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field enable_tsu_timer_comparison_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT             29
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK     0x20000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET            0b0
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field enable_rx_lockup_detected_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__SHIFT               30
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__MASK       0x40000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__RESET              0b0
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__INT_ENABLE__ENABLE_RX_LOCKUP_DETECTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field enable_tx_lockup_detected_interrupt */
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__SHIFT               31
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__MASK       0x80000000U
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__RESET              0b0
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__INT_ENABLE__ENABLE_TX_LOCKUP_DETECTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__INT_ENABLE__TYPE                                               uint32_t
#define EMAC_REGS__INT_ENABLE__WRITE                                           0x00000000U

#endif /* __INT_ENABLE_MACRO__ */


/* macros for int_enable */
#define EMAC_REGS__INST_INT_ENABLE__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::int_disable */
#ifndef __EMAC_REGS__INT_DISABLE_MACRO__
#define __EMAC_REGS__INT_DISABLE_MACRO__

/* macros for field disable_management_done_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT                 0
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH                 1
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MASK        0x00000001U
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__RESET                 0
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field disable_receive_complete_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT                1
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK       0x00000002U
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET                0
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field disable_receive_used_bit_read_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT           2
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH           1
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK  0x00000004U
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET           0
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field disable_transmit_used_bit_read_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT          3
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH          1
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK 0x00000008U
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET          0
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field disable_transmit_buffer_under_run_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT       4
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH       1
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \
                    0x00000010U
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET       0
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
                    5
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
                    0x00000020U
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
                    6
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
                    0x00000040U
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field disable_transmit_complete_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT               7
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH               1
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK      0x00000080U
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET               0
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field disable_usxgmii_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__SHIFT                         8
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__WIDTH                         1
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__MASK                0x00000100U
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__RESET                         0
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__INT_DISABLE__DISABLE_USXGMII_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field disable_link_change_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SHIFT                     9
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WIDTH                     1
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MASK            0x00000200U
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__RESET                     0
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field disable_receive_overrun_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT                10
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH                 1
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MASK        0x00000400U
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__RESET                 0
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field disable_resp_not_ok_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT                    11
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH                     1
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK            0x00000800U
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET                     0
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field disable_pause_frame_with_non_zero_pause_quantum_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \
                    12
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \
                    0x00001000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field disable_pause_time_zero_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT                13
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH                 1
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK        0x00002000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET                 0
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field disable_pause_frame_transmitted_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT        14
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH         1
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK \
                    0x00004000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET         0
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field disable_external_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SHIFT                       15
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WIDTH                        1
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MASK               0x00008000U
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__RESET                        0
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field disable_pcs_auto_negotiation_complete_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT  16
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH   1
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \
                    0x00010000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET   0
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field disable_pcs_link_partner_page_received */
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT           17
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH            1
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK   0x00020000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET            0
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field disable_ptp_delay_req_frame_received */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT             18
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH              1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK     0x00040000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET              0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field disable_ptp_sync_frame_received */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT                  19
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH                   1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MASK          0x00080000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__RESET                   0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field disable_ptp_delay_req_frame_transmitted */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT          20
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH           1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK  0x00100000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET           0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field disable_ptp_sync_frame_transmitted */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT               21
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH                1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK       0x00200000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET                0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field disable_ptp_pdelay_req_frame_received */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT            22
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH             1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK    0x00400000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET             0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00400000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((uint32_t)(src) <<\
                    22) & 0x00400000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00400000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field disable_ptp_pdelay_resp_frame_received */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT           23
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH            1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK   0x00800000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET            0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field disable_ptp_pdelay_req_frame_transmitted */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT         24
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH          1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK 0x01000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET          0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field disable_ptp_pdelay_resp_frame_transmitted */
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT        25
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH         1
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \
                    0x02000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET         0
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field disable_tsu_seconds_register_increment */
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT           26
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH            1
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK   0x04000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET            0
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field disable_rx_lpi_indication_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT              27
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH               1
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MASK      0x08000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__RESET               0
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field disable_wol_event_received_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT             28
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK     0x10000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET              0
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field disable_tsu_timer_comparison_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT           29
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH            1
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK   0x20000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET          0b0
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field disable_rx_lockup_detected_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__SHIFT             30
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__MASK     0x40000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__RESET            0b0
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__INT_DISABLE__DISABLE_RX_LOCKUP_DETECTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field disable_tx_lockup_detected_interrupt */
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__SHIFT             31
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__MASK     0x80000000U
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__RESET            0b0
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__INT_DISABLE__DISABLE_TX_LOCKUP_DETECTED_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__INT_DISABLE__TYPE                                              uint32_t
#define EMAC_REGS__INT_DISABLE__WRITE                                          0x00000000U

#endif /* __INT_DISABLE_MACRO__ */


/* macros for int_disable */
#define EMAC_REGS__INST_INT_DISABLE__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::int_mask */
#ifndef __EMAC_REGS__INT_MASK_MACRO__
#define __EMAC_REGS__INT_MASK_MACRO__

/* macros for field management_done_interrupt_mask */
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SHIFT                       0
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__WIDTH                       1
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__MASK              0x00000001U
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__RESET                       1
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete_interrupt_mask */
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT                      1
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH                      1
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK             0x00000002U
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET                      1
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field receive_used_bit_read_interrupt_mask */
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SHIFT                 2
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__WIDTH                 1
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__MASK        0x00000004U
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__RESET                 1
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read_interrupt_mask */
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SHIFT                3
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__WIDTH                1
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__MASK       0x00000008U
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__RESET                1
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field transmit_buffer_under_run_interrupt_mask */
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SHIFT             4
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__WIDTH             1
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__MASK    0x00000010U
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__RESET             1
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision_mask */
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SHIFT          5
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__WIDTH          1
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__MASK 0x00000020U
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__RESET          1
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error_interrupt_mask */
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT                            6
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH                            1
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK                   0x00000040U
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET                            1
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete_interrupt_mask */
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT                     7
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH                     1
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK            0x00000080U
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET                     1
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field usxgmii_interrupt_mask */
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__SHIFT                               8
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__WIDTH                               1
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__MASK                      0x00000100U
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__RESET                               1
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__INT_MASK__USXGMII_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field link_change_interrupt_mask */
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SHIFT                           9
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__WIDTH                           1
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__MASK                  0x00000200U
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__RESET                           1
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field receive_overrun_interrupt_mask */
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SHIFT                      10
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__WIDTH                       1
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__MASK              0x00000400U
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__RESET                       1
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field resp_not_ok_interrupt_mask */
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT                          11
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH                           1
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK                  0x00000800U
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET                           1
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field pause_frame_with_non_zero_pause_quantum_interrupt_mask */
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SHIFT \
                    12
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__WIDTH \
                    1
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__MASK \
                    0x00001000U
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__RESET \
                    1
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field pause_time_zero_interrupt_mask */
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SHIFT                      13
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__WIDTH                       1
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__MASK              0x00002000U
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__RESET                       1
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field pause_frame_transmitted_interrupt_mask */
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SHIFT              14
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__WIDTH               1
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__MASK      0x00004000U
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__RESET               1
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field external_interrupt_mask */
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SHIFT                             15
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__WIDTH                              1
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__MASK                     0x00008000U
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__RESET                              1
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field pcs_auto_negotiation_complete_interrupt_mask */
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SHIFT        16
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__WIDTH         1
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__MASK \
                    0x00010000U
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__RESET         1
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field pcs_link_partner_page_mask */
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SHIFT                          17
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__WIDTH                           1
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__MASK                  0x00020000U
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__RESET                           1
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field ptp_delay_req_frame_received_mask */
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SHIFT                   18
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__WIDTH                    1
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__MASK           0x00040000U
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__RESET                    1
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field ptp_sync_frame_received_mask */
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SHIFT                        19
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__WIDTH                         1
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__MASK                0x00080000U
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__RESET                         1
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field ptp_delay_req_frame_transmitted_mask */
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT                20
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH                 1
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__MASK        0x00100000U
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__RESET                 1
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field ptp_sync_frame_transmitted_mask */
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SHIFT                     21
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__WIDTH                      1
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__MASK             0x00200000U
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__RESET                      1
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field ptp_pdelay_req_frame_received_mask */
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SHIFT                  22
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__WIDTH                   1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__MASK          0x00400000U
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__RESET                   1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field ptp_pdelay_resp_frame_received_mask */
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SHIFT                 23
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__WIDTH                  1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__MASK         0x00800000U
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__RESET                  1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field ptp_pdelay_req_frame_transmitted_mask */
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT               24
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH                1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__MASK       0x01000000U
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__RESET                1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field ptp_pdelay_resp_frame_transmitted_mask */
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SHIFT              25
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__WIDTH               1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__MASK      0x02000000U
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__RESET               1
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field tsu_seconds_register_increment_mask */
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SHIFT                 26
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__WIDTH                  1
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__MASK         0x04000000U
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__RESET                  1
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field rx_lpi_indication_mask */
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SHIFT                              27
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__WIDTH                               1
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__MASK                      0x08000000U
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__RESET                               1
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field wol_event_received_mask */
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SHIFT                             28
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__WIDTH                              1
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__MASK                     0x10000000U
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__RESET                              1
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field tsu_timer_comparison_mask */
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SHIFT                           29
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__WIDTH                            1
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__MASK                   0x20000000U
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__RESET                            1
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field rx_lockup_detected_mask */
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__SHIFT                             30
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__WIDTH                              1
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__MASK                     0x40000000U
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__RESET                              1
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__INT_MASK__RX_LOCKUP_DETECTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field tx_lockup_detected_mask */
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__SHIFT                             31
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__WIDTH                              1
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__MASK                     0x80000000U
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__RESET                              1
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__INT_MASK__TX_LOCKUP_DETECTED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__INT_MASK__TYPE                                                 uint32_t
#define EMAC_REGS__INT_MASK__READ                                              0xffffffffU

#endif /* __INT_MASK_MACRO__ */


/* macros for int_mask */
#define EMAC_REGS__INST_INT_MASK__NUM                                                    1

/* macros for BlueprintGlobalNameSpace::phy_management */
#ifndef __EMAC_REGS__PHY_MANAGEMENT_MACRO__
#define __EMAC_REGS__PHY_MANAGEMENT_MACRO__

/* macros for field phy_write_read_data */
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__SHIFT                            0
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WIDTH                           16
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MASK                   0x0000ffffU
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__RESET                            0
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field write10 */
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__SHIFT                                       16
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WIDTH                                        2
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MASK                               0x00030000U
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__RESET                                        0
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00030000U) >> 16)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00030000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((uint32_t)(src) <<\
                    16) & 0x00030000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00030000U)))

/* macros for field register_address */
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__SHIFT                              18
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WIDTH                               5
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MASK                      0x007c0000U
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__RESET                               0
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x007c0000U) >> 18)
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x007c0000U)
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007c0000U) | (((uint32_t)(src) <<\
                    18) & 0x007c0000U)
#define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x007c0000U)))

/* macros for field phy_address */
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__SHIFT                                   23
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WIDTH                                    5
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MASK                           0x0f800000U
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__RESET                                    0
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f800000U) >> 23)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x0f800000U)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f800000U) | (((uint32_t)(src) <<\
                    23) & 0x0f800000U)
#define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x0f800000U)))

/* macros for field operation */
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__SHIFT                                     28
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WIDTH                                      2
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MASK                             0x30000000U
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__RESET                                      0
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x30000000U) >> 28)
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x30000000U)
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((uint32_t)(src) <<\
                    28) & 0x30000000U)
#define EMAC_REGS__PHY_MANAGEMENT__OPERATION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field write1 */
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SHIFT                                        30
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WIDTH                                         1
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MASK                                0x40000000U
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__RESET                                         0
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field write0 */
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SHIFT                                        31
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WIDTH                                         1
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MASK                                0x80000000U
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__RESET                                         0
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__PHY_MANAGEMENT__WRITE0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__PHY_MANAGEMENT__TYPE                                           uint32_t
#define EMAC_REGS__PHY_MANAGEMENT__READ                                        0xffffffffU
#define EMAC_REGS__PHY_MANAGEMENT__WRITE                                       0xffffffffU

#endif /* __PHY_MANAGEMENT_MACRO__ */


/* macros for phy_management */
#define EMAC_REGS__INST_PHY_MANAGEMENT__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pause_time */
#ifndef __EMAC_REGS__PAUSE_TIME_MACRO__
#define __EMAC_REGS__PAUSE_TIME_MACRO__

/* macros for field quantum */
#define EMAC_REGS__PAUSE_TIME__QUANTUM__SHIFT                                            0
#define EMAC_REGS__PAUSE_TIME__QUANTUM__WIDTH                                           16
#define EMAC_REGS__PAUSE_TIME__QUANTUM__MASK                                   0x0000ffffU
#define EMAC_REGS__PAUSE_TIME__QUANTUM__RESET                                            0
#define EMAC_REGS__PAUSE_TIME__QUANTUM__READ(src)          ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__SHIFT                                    16
#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__WIDTH                                    16
#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__MASK                            0xffff0000U
#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__RESET                                     0
#define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PAUSE_TIME__TYPE                                               uint32_t
#define EMAC_REGS__PAUSE_TIME__READ                                            0xffffffffU

#endif /* __PAUSE_TIME_MACRO__ */


/* macros for pause_time */
#define EMAC_REGS__INST_PAUSE_TIME__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::tx_pause_quantum */
#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__
#define __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__

/* macros for field quantum */
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__SHIFT                                      0
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WIDTH                                     16
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MASK                             0x0000ffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__RESET                                 0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__READ(src)    ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WRITE(src)   ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field quantum_p1 */
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__SHIFT                                  16
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WIDTH                                  16
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MASK                          0xffff0000U
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__RESET                              0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__TX_PAUSE_QUANTUM__TYPE                                         uint32_t
#define EMAC_REGS__TX_PAUSE_QUANTUM__READ                                      0xffffffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM__WRITE                                     0xffffffffU

#endif /* __TX_PAUSE_QUANTUM_MACRO__ */


/* macros for tx_pause_quantum */
#define EMAC_REGS__INST_TX_PAUSE_QUANTUM__NUM                                            1

/* macros for BlueprintGlobalNameSpace::pbuf_txcutthru */
#ifndef __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__
#define __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__

/* macros for field dma_tx_cutthru_threshold */
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__SHIFT                       0
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WIDTH                      14
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MASK              0x00003fffU
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__RESET                   16383
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((uint32_t)(src) &\
                    0x00003fffU)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field reserved */
#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__SHIFT                                      14
#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__WIDTH                                      17
#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__MASK                              0x7fffc000U
#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__RESET                                       0
#define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fffc000U) >> 14)

/* macros for field dma_tx_cutthru */
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SHIFT                                31
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WIDTH                                 1
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MASK                        0x80000000U
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__RESET                                 0
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__PBUF_TXCUTTHRU__TYPE                                           uint32_t
#define EMAC_REGS__PBUF_TXCUTTHRU__READ                                        0xffffffffU
#define EMAC_REGS__PBUF_TXCUTTHRU__WRITE                                       0xffffffffU

#endif /* __PBUF_TXCUTTHRU_MACRO__ */


/* macros for pbuf_txcutthru */
#define EMAC_REGS__INST_PBUF_TXCUTTHRU__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pbuf_rxcutthru */
#ifndef __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__
#define __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__

/* macros for field dma_rx_cutthru_threshold */
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__SHIFT                       0
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WIDTH                      11
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MASK              0x000007ffU
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__RESET                    2047
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((uint32_t)(src) &\
                    0x000007ffU)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field reserved */
#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__SHIFT                                      11
#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__WIDTH                                      20
#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__MASK                              0x7ffff800U
#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__RESET                                       0
#define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7ffff800U) >> 11)

/* macros for field dma_rx_cutthru */
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SHIFT                                31
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WIDTH                                 1
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MASK                        0x80000000U
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__RESET                                 0
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__PBUF_RXCUTTHRU__TYPE                                           uint32_t
#define EMAC_REGS__PBUF_RXCUTTHRU__READ                                        0xffffffffU
#define EMAC_REGS__PBUF_RXCUTTHRU__WRITE                                       0xffffffffU

#endif /* __PBUF_RXCUTTHRU_MACRO__ */


/* macros for pbuf_rxcutthru */
#define EMAC_REGS__INST_PBUF_RXCUTTHRU__NUM                                              1

/* macros for BlueprintGlobalNameSpace::jumbo_max_length */
#ifndef __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__
#define __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__

/* macros for field jumbo_max_length */
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__SHIFT                             0
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WIDTH                            14
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MASK                    0x00003fffU
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__RESET                         10240
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003fffU) | ((uint32_t)(src) &\
                    0x00003fffU)
#define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00003fffU)))

/* macros for field reserved_31_14 */
#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__SHIFT                              14
#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__WIDTH                              18
#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__MASK                      0xffffc000U
#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__RESET                               0
#define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffc000U) >> 14)
#define EMAC_REGS__JUMBO_MAX_LENGTH__TYPE                                         uint32_t
#define EMAC_REGS__JUMBO_MAX_LENGTH__READ                                      0xffffffffU
#define EMAC_REGS__JUMBO_MAX_LENGTH__WRITE                                     0xffffffffU

#endif /* __JUMBO_MAX_LENGTH_MACRO__ */


/* macros for jumbo_max_length */
#define EMAC_REGS__INST_JUMBO_MAX_LENGTH__NUM                                            1

/* macros for BlueprintGlobalNameSpace::external_fifo_interface */
#ifndef __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__
#define __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__

/* macros for field external_fifo_interface */
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SHIFT               0
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WIDTH               1
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MASK      0x00000001U
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__RESET               0
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_31_1 */
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__SHIFT                         1
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__WIDTH                        31
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__MASK                0xfffffffeU
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__RESET                         0
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffeU) >> 1)
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__TYPE                                  uint32_t
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__READ                               0xffffffffU
#define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__WRITE                              0xffffffffU

#endif /* __EXTERNAL_FIFO_INTERFACE_MACRO__ */


/* macros for external_fifo_interface */
#define EMAC_REGS__INST_EXTERNAL_FIFO_INTERFACE__NUM                                     1

/* macros for BlueprintGlobalNameSpace::hs_mac_config */
#ifndef __EMAC_REGS__HS_MAC_CONFIG_MACRO__
#define __EMAC_REGS__HS_MAC_CONFIG_MACRO__

/* macros for field hs_mac_speed */
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__SHIFT                                    0
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__WIDTH                                    3
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__MASK                           0x00000007U
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__RESET                                    4
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__READ(src)  ((uint32_t)(src) & 0x00000007U)
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__WRITE(src) ((uint32_t)(src) & 0x00000007U)
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((uint32_t)(src) &\
                    0x00000007U)
#define EMAC_REGS__HS_MAC_CONFIG__HS_MAC_SPEED__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000007U)))

/* macros for field nsp_change */
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__SHIFT                                      3
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__WIDTH                                      1
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__MASK                             0x00000008U
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__RESET                                      0
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__HS_MAC_CONFIG__NSP_CHANGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field tx_defer */
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__SHIFT                                        4
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__WIDTH                                        1
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__MASK                               0x00000010U
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__RESET                                        0
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__HS_MAC_CONFIG__TX_DEFER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field preamble_in_crc_tx */
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__SHIFT                              5
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__WIDTH                              2
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__MASK                     0x00000060U
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__RESET                              0
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000060U) >> 5)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000060U)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000060U) | (((uint32_t)(src) <<\
                    5) & 0x00000060U)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_TX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000060U)))

/* macros for field preamble_in_crc_rx */
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__SHIFT                              7
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__WIDTH                              2
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__MASK                     0x00000180U
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__RESET                              0
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000180U) >> 7)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000180U)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000180U) | (((uint32_t)(src) <<\
                    7) & 0x00000180U)
#define EMAC_REGS__HS_MAC_CONFIG__PREAMBLE_IN_CRC_RX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000180U)))

/* macros for field defer_on_linkint_os */
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__SHIFT                             9
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__WIDTH                             1
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__MASK                    0x00000200U
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__RESET                             0
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__HS_MAC_CONFIG__DEFER_ON_LINKINT_OS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field reserved_31_10 */
#define EMAC_REGS__HS_MAC_CONFIG__RESERVED_31_10__SHIFT                                 10
#define EMAC_REGS__HS_MAC_CONFIG__RESERVED_31_10__WIDTH                                 22
#define EMAC_REGS__HS_MAC_CONFIG__RESERVED_31_10__MASK                         0xfffffc00U
#define EMAC_REGS__HS_MAC_CONFIG__RESERVED_31_10__RESET                                  0
#define EMAC_REGS__HS_MAC_CONFIG__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__HS_MAC_CONFIG__TYPE                                            uint32_t
#define EMAC_REGS__HS_MAC_CONFIG__READ                                         0xffffffffU
#define EMAC_REGS__HS_MAC_CONFIG__WRITE                                        0xffffffffU

#endif /* __HS_MAC_CONFIG_MACRO__ */


/* macros for hs_mac_config */
#define EMAC_REGS__INST_HS_MAC_CONFIG__NUM                                               1

/* macros for BlueprintGlobalNameSpace::axi_max_pipeline */
#ifndef __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__
#define __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__

/* macros for field ar2r_max_pipeline */
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__SHIFT                            0
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WIDTH                            8
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MASK                   0x000000ffU
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__RESET                            1
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field aw2w_max_pipeline */
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__SHIFT                            8
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WIDTH                            8
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MASK                   0x0000ff00U
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__RESET                            1
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field use_aw2b_fill */
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SHIFT                               16
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WIDTH                                1
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MASK                       0x00010000U
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__RESET                                0
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_31_17 */
#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED_31_17__RESET                               0
#define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__AXI_MAX_PIPELINE__TYPE                                         uint32_t
#define EMAC_REGS__AXI_MAX_PIPELINE__READ                                      0xffffffffU
#define EMAC_REGS__AXI_MAX_PIPELINE__WRITE                                     0xffffffffU

#endif /* __AXI_MAX_PIPELINE_MACRO__ */


/* macros for axi_max_pipeline */
#define EMAC_REGS__INST_AXI_MAX_PIPELINE__NUM                                            1

/* macros for BlueprintGlobalNameSpace::rsc_control */
#ifndef __EMAC_REGS__RSC_CONTROL_MACRO__
#define __EMAC_REGS__RSC_CONTROL_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__SHIFT                                        0
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__WIDTH                                        1
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__MASK                               0x00000001U
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__RESET                                        0
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__READ(src)      ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__RSC_CONTROL__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rsc_control */
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__SHIFT                                       1
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WIDTH                                      15
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MASK                              0x0000fffeU
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__RESET                                       0
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fffeU) >> 1)
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x0000fffeU)
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000fffeU) | (((uint32_t)(src) <<\
                    1) & 0x0000fffeU)
#define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x0000fffeU)))

/* macros for field rsc_clr_mask */
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SHIFT                                     16
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WIDTH                                      1
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MASK                             0x00010000U
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__RESET                                      0
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_31_17 */
#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__SHIFT                                   17
#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__WIDTH                                   15
#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__MASK                           0xfffe0000U
#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__RESET                                    0
#define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__RSC_CONTROL__TYPE                                              uint32_t
#define EMAC_REGS__RSC_CONTROL__READ                                           0xffffffffU
#define EMAC_REGS__RSC_CONTROL__WRITE                                          0xffffffffU

#endif /* __RSC_CONTROL_MACRO__ */


/* macros for rsc_control */
#define EMAC_REGS__INST_RSC_CONTROL__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::int_moderation */
#ifndef __EMAC_REGS__INT_MODERATION_MACRO__
#define __EMAC_REGS__INT_MODERATION_MACRO__

/* macros for field rx_int_moderation */
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__SHIFT                              0
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WIDTH                              8
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MASK                     0x000000ffU
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__RESET                              0
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field rx_int_mod_thresh */
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__SHIFT                              8
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__WIDTH                              8
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__MASK                     0x0000ff00U
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__RESET                              0
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__INT_MODERATION__RX_INT_MOD_THRESH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field tx_int_moderation */
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__SHIFT                             16
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WIDTH                              8
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MASK                     0x00ff0000U
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__RESET                              0
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field tx_int_mod_thresh */
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__SHIFT                             24
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__WIDTH                              8
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__MASK                     0xff000000U
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__RESET                              0
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__INT_MODERATION__TX_INT_MOD_THRESH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__INT_MODERATION__TYPE                                           uint32_t
#define EMAC_REGS__INT_MODERATION__READ                                        0xffffffffU
#define EMAC_REGS__INT_MODERATION__WRITE                                       0xffffffffU

#endif /* __INT_MODERATION_MACRO__ */


/* macros for int_moderation */
#define EMAC_REGS__INST_INT_MODERATION__NUM                                              1

/* macros for BlueprintGlobalNameSpace::sys_wake_time */
#ifndef __EMAC_REGS__SYS_WAKE_TIME_MACRO__
#define __EMAC_REGS__SYS_WAKE_TIME_MACRO__

/* macros for field sys_wake_time */
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__SHIFT                                   0
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WIDTH                                  16
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MASK                          0x0000ffffU
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__RESET                                   0
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__READ(src) ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__SHIFT                                 16
#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__WIDTH                                 16
#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__MASK                         0xffff0000U
#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__RESET                                  0
#define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__SYS_WAKE_TIME__TYPE                                            uint32_t
#define EMAC_REGS__SYS_WAKE_TIME__READ                                         0xffffffffU
#define EMAC_REGS__SYS_WAKE_TIME__WRITE                                        0xffffffffU

#endif /* __SYS_WAKE_TIME_MACRO__ */


/* macros for sys_wake_time */
#define EMAC_REGS__INST_SYS_WAKE_TIME__NUM                                               1

/* macros for BlueprintGlobalNameSpace::lockup_config */
#ifndef __EMAC_REGS__LOCKUP_CONFIG_MACRO__
#define __EMAC_REGS__LOCKUP_CONFIG_MACRO__

/* macros for field prescaler_value */
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__SHIFT                                 0
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__WIDTH                                16
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__MASK                        0x0000ffffU
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__RESET                            0xFFFF
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__LOCKUP_CONFIG__PRESCALER_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field dma_lockup_time */
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__SHIFT                                16
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__WIDTH                                11
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__MASK                        0x07ff0000U
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__RESET                             0x7FF
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__READ(src) \
                    (((uint32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x07ff0000U)
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x07ff0000U)
#define EMAC_REGS__LOCKUP_CONFIG__DMA_LOCKUP_TIME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x07ff0000U)))

/* macros for field lockup_recovery_en */
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__SHIFT                             27
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__WIDTH                              1
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__MASK                     0x08000000U
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__RESET                              0
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__LOCKUP_CONFIG__LOCKUP_RECOVERY_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field rx_mac_lockup_mon_en */
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__SHIFT                           28
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__WIDTH                            1
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__MASK                   0x10000000U
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__RESET                            0
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__LOCKUP_CONFIG__RX_MAC_LOCKUP_MON_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field rx_dma_lockup_mon_en */
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__SHIFT                           29
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__WIDTH                            1
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__MASK                   0x20000000U
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__RESET                            0
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__LOCKUP_CONFIG__RX_DMA_LOCKUP_MON_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field tx_mac_lockup_mon_en */
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__SHIFT                           30
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__WIDTH                            1
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__MASK                   0x40000000U
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__RESET                            0
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__LOCKUP_CONFIG__TX_MAC_LOCKUP_MON_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field tx_dma_lockup_mon_en */
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__SHIFT                           31
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__WIDTH                            1
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__MASK                   0x80000000U
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__RESET                            0
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__LOCKUP_CONFIG__TX_DMA_LOCKUP_MON_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__LOCKUP_CONFIG__TYPE                                            uint32_t
#define EMAC_REGS__LOCKUP_CONFIG__READ                                         0xffffffffU
#define EMAC_REGS__LOCKUP_CONFIG__WRITE                                        0xffffffffU

#endif /* __LOCKUP_CONFIG_MACRO__ */


/* macros for lockup_config */
#define EMAC_REGS__INST_LOCKUP_CONFIG__NUM                                               1

/* macros for BlueprintGlobalNameSpace::mac_lockup_time */
#ifndef __EMAC_REGS__MAC_LOCKUP_TIME_MACRO__
#define __EMAC_REGS__MAC_LOCKUP_TIME_MACRO__

/* macros for field rx_mac_lockup_time */
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__SHIFT                            0
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__WIDTH                           16
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__MASK                   0x0000ffffU
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__RESET                       0xFFFF
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__MAC_LOCKUP_TIME__RX_MAC_LOCKUP_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field tx_mac_lockup_time */
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__SHIFT                           16
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__WIDTH                           11
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__MASK                   0x07ff0000U
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__RESET                        0x7FF
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__READ(src) \
                    (((uint32_t)(src)\
                    & 0x07ff0000U) >> 16)
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x07ff0000U)
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x07ff0000U)
#define EMAC_REGS__MAC_LOCKUP_TIME__TX_MAC_LOCKUP_TIME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x07ff0000U)))

/* macros for field reserved_31_27 */
#define EMAC_REGS__MAC_LOCKUP_TIME__RESERVED_31_27__SHIFT                               27
#define EMAC_REGS__MAC_LOCKUP_TIME__RESERVED_31_27__WIDTH                                5
#define EMAC_REGS__MAC_LOCKUP_TIME__RESERVED_31_27__MASK                       0xf8000000U
#define EMAC_REGS__MAC_LOCKUP_TIME__RESERVED_31_27__RESET                                0
#define EMAC_REGS__MAC_LOCKUP_TIME__RESERVED_31_27__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf8000000U) >> 27)
#define EMAC_REGS__MAC_LOCKUP_TIME__TYPE                                          uint32_t
#define EMAC_REGS__MAC_LOCKUP_TIME__READ                                       0xffffffffU
#define EMAC_REGS__MAC_LOCKUP_TIME__WRITE                                      0xffffffffU

#endif /* __MAC_LOCKUP_TIME_MACRO__ */


/* macros for mac_lockup_time */
#define EMAC_REGS__INST_MAC_LOCKUP_TIME__NUM                                             1

/* macros for BlueprintGlobalNameSpace::lockup_config3 */
#ifndef __EMAC_REGS__LOCKUP_CONFIG3_MACRO__
#define __EMAC_REGS__LOCKUP_CONFIG3_MACRO__

/* macros for field dma_tx_lockup_en_q_0 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__SHIFT                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__MASK                  0x00000001U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field dma_tx_lockup_en_q_1 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__SHIFT                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__MASK                  0x00000002U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_tx_lockup_en_q_2 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__SHIFT                           2
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__MASK                  0x00000004U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field dma_tx_lockup_en_q_3 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__SHIFT                           3
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__MASK                  0x00000008U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field dma_tx_lockup_en_q_4 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__SHIFT                           4
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__MASK                  0x00000010U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field dma_tx_lockup_en_q_5 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__SHIFT                           5
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__MASK                  0x00000020U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field dma_tx_lockup_en_q_6 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__SHIFT                           6
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__MASK                  0x00000040U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_6__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field dma_tx_lockup_en_q_7 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__SHIFT                           7
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__MASK                  0x00000080U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field dma_tx_lockup_en_q_8 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__SHIFT                           8
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__MASK                  0x00000100U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field dma_tx_lockup_en_q_9 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__SHIFT                           9
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__WIDTH                           1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__MASK                  0x00000200U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__RESET                           0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_9__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field dma_tx_lockup_en_q_10 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__SHIFT                         10
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__MASK                 0x00000400U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_10__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field dma_tx_lockup_en_q_11 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__SHIFT                         11
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__MASK                 0x00000800U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field dma_tx_lockup_en_q_12 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__SHIFT                         12
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__MASK                 0x00001000U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_12__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field dma_tx_lockup_en_q_13 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__SHIFT                         13
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__MASK                 0x00002000U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_13__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field dma_tx_lockup_en_q_14 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__SHIFT                         14
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__MASK                 0x00004000U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field dma_tx_lockup_en_q_15 */
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__SHIFT                         15
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__WIDTH                          1
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__MASK                 0x00008000U
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__RESET                          0
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__LOCKUP_CONFIG3__RESERVED_31_16__SHIFT                                16
#define EMAC_REGS__LOCKUP_CONFIG3__RESERVED_31_16__WIDTH                                16
#define EMAC_REGS__LOCKUP_CONFIG3__RESERVED_31_16__MASK                        0xffff0000U
#define EMAC_REGS__LOCKUP_CONFIG3__RESERVED_31_16__RESET                                 0
#define EMAC_REGS__LOCKUP_CONFIG3__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__LOCKUP_CONFIG3__TYPE                                           uint32_t
#define EMAC_REGS__LOCKUP_CONFIG3__READ                                        0xffffffffU
#define EMAC_REGS__LOCKUP_CONFIG3__WRITE                                       0xffffffffU

#endif /* __LOCKUP_CONFIG3_MACRO__ */


/* macros for lockup_config3 */
#define EMAC_REGS__INST_LOCKUP_CONFIG3__NUM                                              1

/* macros for BlueprintGlobalNameSpace::rx_water_mark */
#ifndef __EMAC_REGS__RX_WATER_MARK_MACRO__
#define __EMAC_REGS__RX_WATER_MARK_MACRO__

/* macros for field rx_high_watermark */
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__SHIFT                               0
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__WIDTH                              16
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__MASK                      0x0000ffffU
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__RESET                          0x0000
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__RX_WATER_MARK__RX_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field rx_low_watermark */
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__SHIFT                               16
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__WIDTH                               16
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__MASK                       0xffff0000U
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__RESET                           0x0000
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__RX_WATER_MARK__RX_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__RX_WATER_MARK__TYPE                                            uint32_t
#define EMAC_REGS__RX_WATER_MARK__READ                                         0xffffffffU
#define EMAC_REGS__RX_WATER_MARK__WRITE                                        0xffffffffU

#endif /* __RX_WATER_MARK_MACRO__ */


/* macros for rx_water_mark */
#define EMAC_REGS__INST_RX_WATER_MARK__NUM                                               1

/* macros for BlueprintGlobalNameSpace::hash_bottom */
#ifndef __EMAC_REGS__HASH_BOTTOM_MACRO__
#define __EMAC_REGS__HASH_BOTTOM_MACRO__

/* macros for field address */
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__SHIFT                                           0
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__WIDTH                                          32
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__MASK                                  0xffffffffU
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__RESET                                           0
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__READ(src)         ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__WRITE(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__HASH_BOTTOM__ADDRESS__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU)))
#define EMAC_REGS__HASH_BOTTOM__TYPE                                              uint32_t
#define EMAC_REGS__HASH_BOTTOM__READ                                           0xffffffffU
#define EMAC_REGS__HASH_BOTTOM__WRITE                                          0xffffffffU

#endif /* __HASH_BOTTOM_MACRO__ */


/* macros for hash_bottom */
#define EMAC_REGS__INST_HASH_BOTTOM__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::hash_top */
#ifndef __EMAC_REGS__HASH_TOP_MACRO__
#define __EMAC_REGS__HASH_TOP_MACRO__

/* macros for field address */
#define EMAC_REGS__HASH_TOP__ADDRESS__SHIFT                                              0
#define EMAC_REGS__HASH_TOP__ADDRESS__WIDTH                                             32
#define EMAC_REGS__HASH_TOP__ADDRESS__MASK                                     0xffffffffU
#define EMAC_REGS__HASH_TOP__ADDRESS__RESET                                              0
#define EMAC_REGS__HASH_TOP__ADDRESS__READ(src)            ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__HASH_TOP__ADDRESS__WRITE(src)           ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__HASH_TOP__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__HASH_TOP__ADDRESS__VERIFY(src)    (!(((uint32_t)(src) & ~0xffffffffU)))
#define EMAC_REGS__HASH_TOP__TYPE                                                 uint32_t
#define EMAC_REGS__HASH_TOP__READ                                              0xffffffffU
#define EMAC_REGS__HASH_TOP__WRITE                                             0xffffffffU

#endif /* __HASH_TOP_MACRO__ */


/* macros for hash_top */
#define EMAC_REGS__INST_HASH_TOP__NUM                                                    1

/* macros for BlueprintGlobalNameSpace::spec_add_bottom */
#ifndef __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__
#define __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__

/* macros for field address */
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__SHIFT                                       0
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WIDTH                                      32
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MASK                              0xffffffffU
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__RESET                                       0
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__READ(src)     ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WRITE(src)    ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__SPEC_ADD_BOTTOM__TYPE                                          uint32_t
#define EMAC_REGS__SPEC_ADD_BOTTOM__READ                                       0xffffffffU
#define EMAC_REGS__SPEC_ADD_BOTTOM__WRITE                                      0xffffffffU

#endif /* __SPEC_ADD_BOTTOM_MACRO__ */


/* macros for spec_add1_bottom */
#define EMAC_REGS__INST_SPEC_ADD1_BOTTOM__NUM                                            1

/* macros for BlueprintGlobalNameSpace::spec_add_top_no_mask */
#ifndef __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__
#define __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__

/* macros for field address */
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__SHIFT                                  0
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WIDTH                                 16
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MASK                         0x0000ffffU
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__RESET                                  0
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field filter_type */
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SHIFT                             16
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WIDTH                              1
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MASK                     0x00010000U
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__RESET                              0
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_31_17 */
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__SHIFT                          17
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__WIDTH                          15
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__MASK                  0xfffe0000U
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__RESET                           0
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__TYPE                                     uint32_t
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__READ                                  0xffffffffU
#define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__WRITE                                 0xffffffffU

#endif /* __SPEC_ADD_TOP_NO_MASK_MACRO__ */


/* macros for spec_add1_top */
#define EMAC_REGS__INST_SPEC_ADD1_TOP__NUM                                               1

/* macros for spec_add2_bottom */
#define EMAC_REGS__INST_SPEC_ADD2_BOTTOM__NUM                                            1

/* macros for BlueprintGlobalNameSpace::spec_add_top */
#ifndef __EMAC_REGS__SPEC_ADD_TOP_MACRO__
#define __EMAC_REGS__SPEC_ADD_TOP_MACRO__

/* macros for field address */
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__SHIFT                                          0
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WIDTH                                         16
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MASK                                 0x0000ffffU
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__RESET                                          0
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__READ(src)        ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WRITE(src)       ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field filter_type */
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SHIFT                                     16
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WIDTH                                      1
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MASK                             0x00010000U
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__RESET                                      0
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_23_17 */
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__SHIFT                                  17
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__WIDTH                                   7
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__MASK                          0x00fe0000U
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__RESET                                   0
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00fe0000U) >> 17)

/* macros for field filter_byte_mask */
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__SHIFT                                24
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WIDTH                                 6
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MASK                        0x3f000000U
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__RESET                                 0
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3f000000U) >> 24)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x3f000000U)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3f000000U) | (((uint32_t)(src) <<\
                    24) & 0x3f000000U)
#define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x3f000000U)))

/* macros for field reserved_31_30 */
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__SHIFT                                  30
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__WIDTH                                   2
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__MASK                          0xc0000000U
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__RESET                                   0
#define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__SPEC_ADD_TOP__TYPE                                             uint32_t
#define EMAC_REGS__SPEC_ADD_TOP__READ                                          0xffffffffU
#define EMAC_REGS__SPEC_ADD_TOP__WRITE                                         0xffffffffU

#endif /* __SPEC_ADD_TOP_MACRO__ */


/* macros for spec_add2_top */
#define EMAC_REGS__INST_SPEC_ADD2_TOP__NUM                                               1

/* macros for spec_add3_bottom */
#define EMAC_REGS__INST_SPEC_ADD3_BOTTOM__NUM                                            1

/* macros for spec_add3_top */
#define EMAC_REGS__INST_SPEC_ADD3_TOP__NUM                                               1

/* macros for spec_add4_bottom */
#define EMAC_REGS__INST_SPEC_ADD4_BOTTOM__NUM                                            1

/* macros for spec_add4_top */
#define EMAC_REGS__INST_SPEC_ADD4_TOP__NUM                                               1

/* macros for BlueprintGlobalNameSpace::spec_type1 */
#ifndef __EMAC_REGS__SPEC_TYPE1_MACRO__
#define __EMAC_REGS__SPEC_TYPE1_MACRO__

/* macros for field match */
#define EMAC_REGS__SPEC_TYPE1__MATCH__SHIFT                                              0
#define EMAC_REGS__SPEC_TYPE1__MATCH__WIDTH                                             16
#define EMAC_REGS__SPEC_TYPE1__MATCH__MASK                                     0x0000ffffU
#define EMAC_REGS__SPEC_TYPE1__MATCH__RESET                                              0
#define EMAC_REGS__SPEC_TYPE1__MATCH__READ(src)            ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE1__MATCH__WRITE(src)           ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE1__MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE1__MATCH__VERIFY(src)    (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__SHIFT                                    16
#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__WIDTH                                    15
#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__MASK                            0x7fff0000U
#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__RESET                                     0
#define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field enable_copy */
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SHIFT                                       31
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WIDTH                                        1
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MASK                               0x80000000U
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__RESET                                        0
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SPEC_TYPE1__TYPE                                               uint32_t
#define EMAC_REGS__SPEC_TYPE1__READ                                            0xffffffffU
#define EMAC_REGS__SPEC_TYPE1__WRITE                                           0xffffffffU

#endif /* __SPEC_TYPE1_MACRO__ */


/* macros for spec_type1 */
#define EMAC_REGS__INST_SPEC_TYPE1__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::spec_type2 */
#ifndef __EMAC_REGS__SPEC_TYPE2_MACRO__
#define __EMAC_REGS__SPEC_TYPE2_MACRO__

/* macros for field match */
#define EMAC_REGS__SPEC_TYPE2__MATCH__SHIFT                                              0
#define EMAC_REGS__SPEC_TYPE2__MATCH__WIDTH                                             16
#define EMAC_REGS__SPEC_TYPE2__MATCH__MASK                                     0x0000ffffU
#define EMAC_REGS__SPEC_TYPE2__MATCH__RESET                                              0
#define EMAC_REGS__SPEC_TYPE2__MATCH__READ(src)            ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE2__MATCH__WRITE(src)           ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE2__MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE2__MATCH__VERIFY(src)    (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__SHIFT                                    16
#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__WIDTH                                    15
#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__MASK                            0x7fff0000U
#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__RESET                                     0
#define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field enable_copy */
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SHIFT                                       31
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WIDTH                                        1
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MASK                               0x80000000U
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__RESET                                        0
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SPEC_TYPE2__TYPE                                               uint32_t
#define EMAC_REGS__SPEC_TYPE2__READ                                            0xffffffffU
#define EMAC_REGS__SPEC_TYPE2__WRITE                                           0xffffffffU

#endif /* __SPEC_TYPE2_MACRO__ */


/* macros for spec_type2 */
#define EMAC_REGS__INST_SPEC_TYPE2__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::spec_type3 */
#ifndef __EMAC_REGS__SPEC_TYPE3_MACRO__
#define __EMAC_REGS__SPEC_TYPE3_MACRO__

/* macros for field match */
#define EMAC_REGS__SPEC_TYPE3__MATCH__SHIFT                                              0
#define EMAC_REGS__SPEC_TYPE3__MATCH__WIDTH                                             16
#define EMAC_REGS__SPEC_TYPE3__MATCH__MASK                                     0x0000ffffU
#define EMAC_REGS__SPEC_TYPE3__MATCH__RESET                                              0
#define EMAC_REGS__SPEC_TYPE3__MATCH__READ(src)            ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE3__MATCH__WRITE(src)           ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE3__MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE3__MATCH__VERIFY(src)    (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__SHIFT                                    16
#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__WIDTH                                    15
#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__MASK                            0x7fff0000U
#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__RESET                                     0
#define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field enable_copy */
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SHIFT                                       31
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WIDTH                                        1
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MASK                               0x80000000U
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__RESET                                        0
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SPEC_TYPE3__TYPE                                               uint32_t
#define EMAC_REGS__SPEC_TYPE3__READ                                            0xffffffffU
#define EMAC_REGS__SPEC_TYPE3__WRITE                                           0xffffffffU

#endif /* __SPEC_TYPE3_MACRO__ */


/* macros for spec_type3 */
#define EMAC_REGS__INST_SPEC_TYPE3__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::spec_type4 */
#ifndef __EMAC_REGS__SPEC_TYPE4_MACRO__
#define __EMAC_REGS__SPEC_TYPE4_MACRO__

/* macros for field match */
#define EMAC_REGS__SPEC_TYPE4__MATCH__SHIFT                                              0
#define EMAC_REGS__SPEC_TYPE4__MATCH__WIDTH                                             16
#define EMAC_REGS__SPEC_TYPE4__MATCH__MASK                                     0x0000ffffU
#define EMAC_REGS__SPEC_TYPE4__MATCH__RESET                                              0
#define EMAC_REGS__SPEC_TYPE4__MATCH__READ(src)            ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE4__MATCH__WRITE(src)           ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE4__MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SPEC_TYPE4__MATCH__VERIFY(src)    (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__SHIFT                                    16
#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__WIDTH                                    15
#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__MASK                            0x7fff0000U
#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__RESET                                     0
#define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field enable_copy */
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SHIFT                                       31
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WIDTH                                        1
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MASK                               0x80000000U
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__RESET                                        0
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SPEC_TYPE4__TYPE                                               uint32_t
#define EMAC_REGS__SPEC_TYPE4__READ                                            0xffffffffU
#define EMAC_REGS__SPEC_TYPE4__WRITE                                           0xffffffffU

#endif /* __SPEC_TYPE4_MACRO__ */


/* macros for spec_type4 */
#define EMAC_REGS__INST_SPEC_TYPE4__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::wol_register */
#ifndef __EMAC_REGS__WOL_REGISTER_MACRO__
#define __EMAC_REGS__WOL_REGISTER_MACRO__

/* macros for field addr */
#define EMAC_REGS__WOL_REGISTER__ADDR__SHIFT                                             0
#define EMAC_REGS__WOL_REGISTER__ADDR__WIDTH                                            16
#define EMAC_REGS__WOL_REGISTER__ADDR__MASK                                    0x0000ffffU
#define EMAC_REGS__WOL_REGISTER__ADDR__RESET                                             0
#define EMAC_REGS__WOL_REGISTER__ADDR__READ(src)           ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__WOL_REGISTER__ADDR__WRITE(src)          ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__WOL_REGISTER__ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__WOL_REGISTER__ADDR__VERIFY(src)   (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field wol_mask_0 */
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SHIFT                                      16
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WIDTH                                       1
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MASK                              0x00010000U
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__RESET                                       0
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field wol_mask_1 */
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SHIFT                                      17
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WIDTH                                       1
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MASK                              0x00020000U
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__RESET                                       0
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field wol_mask_2 */
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SHIFT                                      18
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WIDTH                                       1
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MASK                              0x00040000U
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__RESET                                       0
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field wol_mask_3 */
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SHIFT                                      19
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WIDTH                                       1
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MASK                              0x00080000U
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__RESET                                       0
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field reserved_31_20 */
#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__SHIFT                                  20
#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__WIDTH                                  12
#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__MASK                          0xfff00000U
#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__RESET                                   0
#define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfff00000U) >> 20)
#define EMAC_REGS__WOL_REGISTER__TYPE                                             uint32_t
#define EMAC_REGS__WOL_REGISTER__READ                                          0xffffffffU
#define EMAC_REGS__WOL_REGISTER__WRITE                                         0xffffffffU

#endif /* __WOL_REGISTER_MACRO__ */


/* macros for wol_register */
#define EMAC_REGS__INST_WOL_REGISTER__NUM                                                1

/* macros for BlueprintGlobalNameSpace::stretch_ratio */
#ifndef __EMAC_REGS__STRETCH_RATIO_MACRO__
#define __EMAC_REGS__STRETCH_RATIO_MACRO__

/* macros for field ipg_stretch */
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__SHIFT                                     0
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WIDTH                                    16
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MASK                            0x0000ffffU
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__RESET                                     0
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__READ(src)   ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WRITE(src)  ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__SHIFT                                 16
#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__WIDTH                                 16
#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__MASK                         0xffff0000U
#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__RESET                                  0
#define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__STRETCH_RATIO__TYPE                                            uint32_t
#define EMAC_REGS__STRETCH_RATIO__READ                                         0xffffffffU
#define EMAC_REGS__STRETCH_RATIO__WRITE                                        0xffffffffU

#endif /* __STRETCH_RATIO_MACRO__ */


/* macros for stretch_ratio */
#define EMAC_REGS__INST_STRETCH_RATIO__NUM                                               1

/* macros for BlueprintGlobalNameSpace::stacked_vlan */
#ifndef __EMAC_REGS__STACKED_VLAN_MACRO__
#define __EMAC_REGS__STACKED_VLAN_MACRO__

/* macros for field match */
#define EMAC_REGS__STACKED_VLAN__MATCH__SHIFT                                            0
#define EMAC_REGS__STACKED_VLAN__MATCH__WIDTH                                           16
#define EMAC_REGS__STACKED_VLAN__MATCH__MASK                                   0x0000ffffU
#define EMAC_REGS__STACKED_VLAN__MATCH__RESET                                       0x0000
#define EMAC_REGS__STACKED_VLAN__MATCH__READ(src)          ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__STACKED_VLAN__MATCH__WRITE(src)         ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__STACKED_VLAN__MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__STACKED_VLAN__MATCH__VERIFY(src)  (!(((uint32_t)(src) & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__SHIFT                                  16
#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__WIDTH                                  15
#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__MASK                          0x7fff0000U
#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__RESET                                   0
#define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field enable_processing */
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SHIFT                               31
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WIDTH                                1
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MASK                       0x80000000U
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__RESET                                0
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__STACKED_VLAN__TYPE                                             uint32_t
#define EMAC_REGS__STACKED_VLAN__READ                                          0xffffffffU
#define EMAC_REGS__STACKED_VLAN__WRITE                                         0xffffffffU

#endif /* __STACKED_VLAN_MACRO__ */


/* macros for stacked_vlan */
#define EMAC_REGS__INST_STACKED_VLAN__NUM                                                1

/* macros for BlueprintGlobalNameSpace::tx_pfc_pause */
#ifndef __EMAC_REGS__TX_PFC_PAUSE_MACRO__
#define __EMAC_REGS__TX_PFC_PAUSE_MACRO__

/* macros for field vector_enable */
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__SHIFT                                    0
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WIDTH                                    8
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MASK                           0x000000ffU
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__RESET                                    0
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__READ(src)  ((uint32_t)(src) & 0x000000ffU)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WRITE(src) ((uint32_t)(src) & 0x000000ffU)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field vector */
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__SHIFT                                           8
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WIDTH                                           8
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MASK                                  0x0000ff00U
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__RESET                                           0
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__READ(src)  (((uint32_t)(src) & 0x0000ff00U) >> 8)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WRITE(src) (((uint32_t)(src) << 8) & 0x0000ff00U)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__TX_PFC_PAUSE__VECTOR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__SHIFT                                  16
#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__WIDTH                                  16
#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__MASK                          0xffff0000U
#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__RESET                                   0
#define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_PFC_PAUSE__TYPE                                             uint32_t
#define EMAC_REGS__TX_PFC_PAUSE__READ                                          0xffffffffU
#define EMAC_REGS__TX_PFC_PAUSE__WRITE                                         0xffffffffU

#endif /* __TX_PFC_PAUSE_MACRO__ */


/* macros for tx_pfc_pause */
#define EMAC_REGS__INST_TX_PFC_PAUSE__NUM                                                1

/* macros for BlueprintGlobalNameSpace::mask_add1_bottom */
#ifndef __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__
#define __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__

/* macros for field address_mask */
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__SHIFT                                 0
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WIDTH                                32
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MASK                        0xffffffffU
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__RESET                                 0
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__MASK_ADD1_BOTTOM__TYPE                                         uint32_t
#define EMAC_REGS__MASK_ADD1_BOTTOM__READ                                      0xffffffffU
#define EMAC_REGS__MASK_ADD1_BOTTOM__WRITE                                     0xffffffffU

#endif /* __MASK_ADD1_BOTTOM_MACRO__ */


/* macros for mask_add1_bottom */
#define EMAC_REGS__INST_MASK_ADD1_BOTTOM__NUM                                            1

/* macros for BlueprintGlobalNameSpace::mask_add1_top */
#ifndef __EMAC_REGS__MASK_ADD1_TOP_MACRO__
#define __EMAC_REGS__MASK_ADD1_TOP_MACRO__

/* macros for field address_mask */
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__SHIFT                                    0
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WIDTH                                   16
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MASK                           0x0000ffffU
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__RESET                                    0
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__READ(src)  ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WRITE(src) ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__SHIFT                                 16
#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__WIDTH                                 16
#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__MASK                         0xffff0000U
#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__RESET                                  0
#define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__MASK_ADD1_TOP__TYPE                                            uint32_t
#define EMAC_REGS__MASK_ADD1_TOP__READ                                         0xffffffffU
#define EMAC_REGS__MASK_ADD1_TOP__WRITE                                        0xffffffffU

#endif /* __MASK_ADD1_TOP_MACRO__ */


/* macros for mask_add1_top */
#define EMAC_REGS__INST_MASK_ADD1_TOP__NUM                                               1

/* macros for BlueprintGlobalNameSpace::dma_addr_or_mask */
#ifndef __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__
#define __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__

/* macros for field mask_enable */
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__SHIFT                                  0
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WIDTH                                  4
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MASK                         0x0000000fU
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__RESET                                  0
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field reserved_27_4 */
#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__SHIFT                                4
#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__WIDTH                               24
#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__MASK                       0x0ffffff0U
#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__RESET                                0
#define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0ffffff0U) >> 4)

/* macros for field mask_value */
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__SHIFT                                  28
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WIDTH                                   4
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MASK                          0xf0000000U
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__RESET                                   0
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__DMA_ADDR_OR_MASK__TYPE                                         uint32_t
#define EMAC_REGS__DMA_ADDR_OR_MASK__READ                                      0xffffffffU
#define EMAC_REGS__DMA_ADDR_OR_MASK__WRITE                                     0xffffffffU

#endif /* __DMA_ADDR_OR_MASK_MACRO__ */


/* macros for dma_addr_or_mask */
#define EMAC_REGS__INST_DMA_ADDR_OR_MASK__NUM                                            1

/* macros for BlueprintGlobalNameSpace::rx_ptp_unicast */
#ifndef __EMAC_REGS__RX_PTP_UNICAST_MACRO__
#define __EMAC_REGS__RX_PTP_UNICAST_MACRO__

/* macros for field address */
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__SHIFT                                        0
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WIDTH                                       32
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MASK                               0xffffffffU
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__RESET                                        0
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WRITE(src)     ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__RX_PTP_UNICAST__TYPE                                           uint32_t
#define EMAC_REGS__RX_PTP_UNICAST__READ                                        0xffffffffU
#define EMAC_REGS__RX_PTP_UNICAST__WRITE                                       0xffffffffU

#endif /* __RX_PTP_UNICAST_MACRO__ */


/* macros for rx_ptp_unicast */
#define EMAC_REGS__INST_RX_PTP_UNICAST__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tx_ptp_unicast */
#ifndef __EMAC_REGS__TX_PTP_UNICAST_MACRO__
#define __EMAC_REGS__TX_PTP_UNICAST_MACRO__

/* macros for field address */
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__SHIFT                                        0
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WIDTH                                       32
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MASK                               0xffffffffU
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__RESET                                        0
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WRITE(src)     ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__TX_PTP_UNICAST__TYPE                                           uint32_t
#define EMAC_REGS__TX_PTP_UNICAST__READ                                        0xffffffffU
#define EMAC_REGS__TX_PTP_UNICAST__WRITE                                       0xffffffffU

#endif /* __TX_PTP_UNICAST_MACRO__ */


/* macros for tx_ptp_unicast */
#define EMAC_REGS__INST_TX_PTP_UNICAST__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_nsec_cmp */
#ifndef __EMAC_REGS__TSU_NSEC_CMP_MACRO__
#define __EMAC_REGS__TSU_NSEC_CMP_MACRO__

/* macros for field comparison_value */
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__SHIFT                                 0
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WIDTH                                22
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MASK                        0x003fffffU
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__RESET                                 0
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x003fffffU)
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x003fffffU)
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003fffffU) | ((uint32_t)(src) &\
                    0x003fffffU)
#define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x003fffffU)))

/* macros for field reserved_31_22 */
#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__SHIFT                                  22
#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__WIDTH                                  10
#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__MASK                          0xffc00000U
#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__RESET                                   0
#define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffc00000U) >> 22)
#define EMAC_REGS__TSU_NSEC_CMP__TYPE                                             uint32_t
#define EMAC_REGS__TSU_NSEC_CMP__READ                                          0xffffffffU
#define EMAC_REGS__TSU_NSEC_CMP__WRITE                                         0xffffffffU

#endif /* __TSU_NSEC_CMP_MACRO__ */


/* macros for tsu_nsec_cmp */
#define EMAC_REGS__INST_TSU_NSEC_CMP__NUM                                                1

/* macros for BlueprintGlobalNameSpace::tsu_sec_cmp */
#ifndef __EMAC_REGS__TSU_SEC_CMP_MACRO__
#define __EMAC_REGS__TSU_SEC_CMP_MACRO__

/* macros for field comparison_value */
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__SHIFT                                  0
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WIDTH                                 32
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MASK                         0xffffffffU
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__RESET                                  0
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__TSU_SEC_CMP__TYPE                                              uint32_t
#define EMAC_REGS__TSU_SEC_CMP__READ                                           0xffffffffU
#define EMAC_REGS__TSU_SEC_CMP__WRITE                                          0xffffffffU

#endif /* __TSU_SEC_CMP_MACRO__ */


/* macros for tsu_sec_cmp */
#define EMAC_REGS__INST_TSU_SEC_CMP__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::tsu_msb_sec_cmp */
#ifndef __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__
#define __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__

/* macros for field comparison_value */
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__SHIFT                              0
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WIDTH                             16
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MASK                     0x0000ffffU
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__RESET                              0
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__SHIFT                               16
#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__WIDTH                               16
#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__MASK                       0xffff0000U
#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__RESET                                0
#define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_MSB_SEC_CMP__TYPE                                          uint32_t
#define EMAC_REGS__TSU_MSB_SEC_CMP__READ                                       0xffffffffU
#define EMAC_REGS__TSU_MSB_SEC_CMP__WRITE                                      0xffffffffU

#endif /* __TSU_MSB_SEC_CMP_MACRO__ */


/* macros for tsu_msb_sec_cmp */
#define EMAC_REGS__INST_TSU_MSB_SEC_CMP__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_tx_msb_sec */
#ifndef __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__

/* macros for field timer_seconds */
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__SHIFT                              0
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__WIDTH                             16
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__MASK                     0x0000ffffU
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__RESET                              0
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__SHIFT                            16
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__WIDTH                            16
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__MASK                    0xffff0000U
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__RESET                             0
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TYPE                                       uint32_t
#define EMAC_REGS__TSU_PTP_TX_MSB_SEC__READ                                    0xffffffffU

#endif /* __TSU_PTP_TX_MSB_SEC_MACRO__ */


/* macros for tsu_ptp_tx_msb_sec */
#define EMAC_REGS__INST_TSU_PTP_TX_MSB_SEC__NUM                                          1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_rx_msb_sec */
#ifndef __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__

/* macros for field timer_seconds */
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__SHIFT                              0
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__WIDTH                             16
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__MASK                     0x0000ffffU
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__RESET                              0
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__SHIFT                            16
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__WIDTH                            16
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__MASK                    0xffff0000U
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__RESET                             0
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TYPE                                       uint32_t
#define EMAC_REGS__TSU_PTP_RX_MSB_SEC__READ                                    0xffffffffU

#endif /* __TSU_PTP_RX_MSB_SEC_MACRO__ */


/* macros for tsu_ptp_rx_msb_sec */
#define EMAC_REGS__INST_TSU_PTP_RX_MSB_SEC__NUM                                          1

/* macros for BlueprintGlobalNameSpace::tsu_peer_tx_msb_sec */
#ifndef __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__

/* macros for field timer_seconds */
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__SHIFT                             0
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__WIDTH                            16
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__MASK                    0x0000ffffU
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__RESET                             0
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__SHIFT                           16
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__WIDTH                           16
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__MASK                   0xffff0000U
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__RESET                            0
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TYPE                                      uint32_t
#define EMAC_REGS__TSU_PEER_TX_MSB_SEC__READ                                   0xffffffffU

#endif /* __TSU_PEER_TX_MSB_SEC_MACRO__ */


/* macros for tsu_peer_tx_msb_sec */
#define EMAC_REGS__INST_TSU_PEER_TX_MSB_SEC__NUM                                         1

/* macros for BlueprintGlobalNameSpace::tsu_peer_rx_msb_sec */
#ifndef __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__

/* macros for field timer_seconds */
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__SHIFT                             0
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__WIDTH                            16
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__MASK                    0x0000ffffU
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__RESET                             0
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__SHIFT                           16
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__WIDTH                           16
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__MASK                   0xffff0000U
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__RESET                            0
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TYPE                                      uint32_t
#define EMAC_REGS__TSU_PEER_RX_MSB_SEC__READ                                   0xffffffffU

#endif /* __TSU_PEER_RX_MSB_SEC_MACRO__ */


/* macros for tsu_peer_rx_msb_sec */
#define EMAC_REGS__INST_TSU_PEER_RX_MSB_SEC__NUM                                         1

/* macros for BlueprintGlobalNameSpace::dpram_fill_dbg */
#ifndef __EMAC_REGS__DPRAM_FILL_DBG_MACRO__
#define __EMAC_REGS__DPRAM_FILL_DBG_MACRO__

/* macros for field dma_tx_rx_fill_level_select */
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SHIFT                    0
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WIDTH                    1
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MASK           0x00000001U
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__RESET                    0
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_3_1 */
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__SHIFT                                   1
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__WIDTH                                   3
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__MASK                          0x0000000eU
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__RESET                                   0
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000000eU) >> 1)

/* macros for field dma_tx_q_fill_level_select */
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__SHIFT                     4
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WIDTH                     4
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MASK            0x000000f0U
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__RESET                     0
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field reserved_15_8 */
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__SHIFT                                  8
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__WIDTH                                  8
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__MASK                         0x0000ff00U
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__RESET                                  0
#define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field dma_tx_rx_fill_level */
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__SHIFT                          16
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__WIDTH                          16
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__MASK                  0xffff0000U
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__RESET                           0
#define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__DPRAM_FILL_DBG__TYPE                                           uint32_t
#define EMAC_REGS__DPRAM_FILL_DBG__READ                                        0xffffffffU
#define EMAC_REGS__DPRAM_FILL_DBG__WRITE                                       0xffffffffU

#endif /* __DPRAM_FILL_DBG_MACRO__ */


/* macros for dpram_fill_dbg */
#define EMAC_REGS__INST_DPRAM_FILL_DBG__NUM                                              1

/* macros for BlueprintGlobalNameSpace::revision_reg */
#ifndef __EMAC_REGS__REVISION_REG_MACRO__
#define __EMAC_REGS__REVISION_REG_MACRO__

/* macros for field module_revision */
#define EMAC_REGS__REVISION_REG__MODULE_REVISION__SHIFT                                  0
#define EMAC_REGS__REVISION_REG__MODULE_REVISION__WIDTH                                 16
#define EMAC_REGS__REVISION_REG__MODULE_REVISION__MASK                         0x0000ffffU
#define EMAC_REGS__REVISION_REG__MODULE_REVISION__RESET                                512
#define EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field module_identification_number */
#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__SHIFT                    16
#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__WIDTH                    12
#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__MASK            0x0fff0000U
#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__RESET                     7
#define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0fff0000U) >> 16)

/* macros for field fix_number */
#define EMAC_REGS__REVISION_REG__FIX_NUMBER__SHIFT                                      28
#define EMAC_REGS__REVISION_REG__FIX_NUMBER__WIDTH                                       4
#define EMAC_REGS__REVISION_REG__FIX_NUMBER__MASK                              0xf0000000U
#define EMAC_REGS__REVISION_REG__FIX_NUMBER__RESET                                       0
#define EMAC_REGS__REVISION_REG__FIX_NUMBER__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__REVISION_REG__TYPE                                             uint32_t
#define EMAC_REGS__REVISION_REG__READ                                          0xffffffffU

#endif /* __REVISION_REG_MACRO__ */


/* macros for revision_reg */
#define EMAC_REGS__INST_REVISION_REG__NUM                                                1

/* macros for BlueprintGlobalNameSpace::octets_txed_bottom */
#ifndef __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__
#define __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__

/* macros for field count */
#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__SHIFT                                      0
#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__WIDTH                                     32
#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__MASK                             0xffffffffU
#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__RESET                                      0
#define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__READ(src)    ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__OCTETS_TXED_BOTTOM__TYPE                                       uint32_t
#define EMAC_REGS__OCTETS_TXED_BOTTOM__READ                                    0xffffffffU
#define EMAC_REGS__OCTETS_TXED_BOTTOM__RCLR                                    0xffffffffU

#endif /* __OCTETS_TXED_BOTTOM_MACRO__ */


/* macros for octets_txed_bottom */
#define EMAC_REGS__INST_OCTETS_TXED_BOTTOM__NUM                                          1

/* macros for BlueprintGlobalNameSpace::octets_txed_top */
#ifndef __EMAC_REGS__OCTETS_TXED_TOP_MACRO__
#define __EMAC_REGS__OCTETS_TXED_TOP_MACRO__

/* macros for field count */
#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__SHIFT                                         0
#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__WIDTH                                        16
#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__MASK                                0x0000ffffU
#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__RESET                                         0
#define EMAC_REGS__OCTETS_TXED_TOP__COUNT__READ(src)       ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__SHIFT                               16
#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__WIDTH                               16
#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__MASK                       0xffff0000U
#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__RESET                                0
#define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__OCTETS_TXED_TOP__TYPE                                          uint32_t
#define EMAC_REGS__OCTETS_TXED_TOP__READ                                       0xffffffffU
#define EMAC_REGS__OCTETS_TXED_TOP__RCLR                                       0x0000ffffU

#endif /* __OCTETS_TXED_TOP_MACRO__ */


/* macros for octets_txed_top */
#define EMAC_REGS__INST_OCTETS_TXED_TOP__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_txed_ok */
#ifndef __EMAC_REGS__FRAMES_TXED_OK_MACRO__
#define __EMAC_REGS__FRAMES_TXED_OK_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_OK__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_TXED_OK__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_TXED_OK__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_TXED_OK__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_TXED_OK__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_OK__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_TXED_OK__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_TXED_OK__RCLR                                        0xffffffffU

#endif /* __FRAMES_TXED_OK_MACRO__ */


/* macros for frames_txed_ok */
#define EMAC_REGS__INST_FRAMES_TXED_OK__NUM                                              1

/* macros for BlueprintGlobalNameSpace::broadcast_txed */
#ifndef __EMAC_REGS__BROADCAST_TXED_MACRO__
#define __EMAC_REGS__BROADCAST_TXED_MACRO__

/* macros for field count */
#define EMAC_REGS__BROADCAST_TXED__COUNT__SHIFT                                          0
#define EMAC_REGS__BROADCAST_TXED__COUNT__WIDTH                                         32
#define EMAC_REGS__BROADCAST_TXED__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__BROADCAST_TXED__COUNT__RESET                                          0
#define EMAC_REGS__BROADCAST_TXED__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__BROADCAST_TXED__TYPE                                           uint32_t
#define EMAC_REGS__BROADCAST_TXED__READ                                        0xffffffffU
#define EMAC_REGS__BROADCAST_TXED__RCLR                                        0xffffffffU

#endif /* __BROADCAST_TXED_MACRO__ */


/* macros for broadcast_txed */
#define EMAC_REGS__INST_BROADCAST_TXED__NUM                                              1

/* macros for BlueprintGlobalNameSpace::multicast_txed */
#ifndef __EMAC_REGS__MULTICAST_TXED_MACRO__
#define __EMAC_REGS__MULTICAST_TXED_MACRO__

/* macros for field count */
#define EMAC_REGS__MULTICAST_TXED__COUNT__SHIFT                                          0
#define EMAC_REGS__MULTICAST_TXED__COUNT__WIDTH                                         32
#define EMAC_REGS__MULTICAST_TXED__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__MULTICAST_TXED__COUNT__RESET                                          0
#define EMAC_REGS__MULTICAST_TXED__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__MULTICAST_TXED__TYPE                                           uint32_t
#define EMAC_REGS__MULTICAST_TXED__READ                                        0xffffffffU
#define EMAC_REGS__MULTICAST_TXED__RCLR                                        0xffffffffU

#endif /* __MULTICAST_TXED_MACRO__ */


/* macros for multicast_txed */
#define EMAC_REGS__INST_MULTICAST_TXED__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pause_frames_txed */
#ifndef __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__
#define __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__

/* macros for field count */
#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__SHIFT                                       0
#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__WIDTH                                      16
#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__MASK                              0x0000ffffU
#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__RESET                                       0
#define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__READ(src)     ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__SHIFT                             16
#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__WIDTH                             16
#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__MASK                     0xffff0000U
#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__RESET                              0
#define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PAUSE_FRAMES_TXED__TYPE                                        uint32_t
#define EMAC_REGS__PAUSE_FRAMES_TXED__READ                                     0xffffffffU
#define EMAC_REGS__PAUSE_FRAMES_TXED__RCLR                                     0x0000ffffU

#endif /* __PAUSE_FRAMES_TXED_MACRO__ */


/* macros for pause_frames_txed */
#define EMAC_REGS__INST_PAUSE_FRAMES_TXED__NUM                                           1

/* macros for BlueprintGlobalNameSpace::frames_txed_64 */
#ifndef __EMAC_REGS__FRAMES_TXED_64_MACRO__
#define __EMAC_REGS__FRAMES_TXED_64_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_64__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_TXED_64__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_TXED_64__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_TXED_64__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_TXED_64__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_64__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_TXED_64__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_TXED_64__RCLR                                        0xffffffffU

#endif /* __FRAMES_TXED_64_MACRO__ */


/* macros for frames_txed_64 */
#define EMAC_REGS__INST_FRAMES_TXED_64__NUM                                              1

/* macros for BlueprintGlobalNameSpace::frames_txed_65 */
#ifndef __EMAC_REGS__FRAMES_TXED_65_MACRO__
#define __EMAC_REGS__FRAMES_TXED_65_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_65__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_TXED_65__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_TXED_65__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_TXED_65__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_TXED_65__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_65__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_TXED_65__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_TXED_65__RCLR                                        0xffffffffU

#endif /* __FRAMES_TXED_65_MACRO__ */


/* macros for frames_txed_65 */
#define EMAC_REGS__INST_FRAMES_TXED_65__NUM                                              1

/* macros for BlueprintGlobalNameSpace::frames_txed_128 */
#ifndef __EMAC_REGS__FRAMES_TXED_128_MACRO__
#define __EMAC_REGS__FRAMES_TXED_128_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_128__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_TXED_128__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_TXED_128__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_TXED_128__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_TXED_128__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_128__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_TXED_128__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_TXED_128__RCLR                                       0xffffffffU

#endif /* __FRAMES_TXED_128_MACRO__ */


/* macros for frames_txed_128 */
#define EMAC_REGS__INST_FRAMES_TXED_128__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_txed_256 */
#ifndef __EMAC_REGS__FRAMES_TXED_256_MACRO__
#define __EMAC_REGS__FRAMES_TXED_256_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_256__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_TXED_256__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_TXED_256__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_TXED_256__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_TXED_256__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_256__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_TXED_256__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_TXED_256__RCLR                                       0xffffffffU

#endif /* __FRAMES_TXED_256_MACRO__ */


/* macros for frames_txed_256 */
#define EMAC_REGS__INST_FRAMES_TXED_256__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_txed_512 */
#ifndef __EMAC_REGS__FRAMES_TXED_512_MACRO__
#define __EMAC_REGS__FRAMES_TXED_512_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_512__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_TXED_512__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_TXED_512__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_TXED_512__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_TXED_512__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_512__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_TXED_512__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_TXED_512__RCLR                                       0xffffffffU

#endif /* __FRAMES_TXED_512_MACRO__ */


/* macros for frames_txed_512 */
#define EMAC_REGS__INST_FRAMES_TXED_512__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_txed_1024 */
#ifndef __EMAC_REGS__FRAMES_TXED_1024_MACRO__
#define __EMAC_REGS__FRAMES_TXED_1024_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_1024__COUNT__SHIFT                                        0
#define EMAC_REGS__FRAMES_TXED_1024__COUNT__WIDTH                                       32
#define EMAC_REGS__FRAMES_TXED_1024__COUNT__MASK                               0xffffffffU
#define EMAC_REGS__FRAMES_TXED_1024__COUNT__RESET                                        0
#define EMAC_REGS__FRAMES_TXED_1024__COUNT__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_1024__TYPE                                         uint32_t
#define EMAC_REGS__FRAMES_TXED_1024__READ                                      0xffffffffU
#define EMAC_REGS__FRAMES_TXED_1024__RCLR                                      0xffffffffU

#endif /* __FRAMES_TXED_1024_MACRO__ */


/* macros for frames_txed_1024 */
#define EMAC_REGS__INST_FRAMES_TXED_1024__NUM                                            1

/* macros for BlueprintGlobalNameSpace::frames_txed_1519 */
#ifndef __EMAC_REGS__FRAMES_TXED_1519_MACRO__
#define __EMAC_REGS__FRAMES_TXED_1519_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_TXED_1519__COUNT__SHIFT                                        0
#define EMAC_REGS__FRAMES_TXED_1519__COUNT__WIDTH                                       32
#define EMAC_REGS__FRAMES_TXED_1519__COUNT__MASK                               0xffffffffU
#define EMAC_REGS__FRAMES_TXED_1519__COUNT__RESET                                        0
#define EMAC_REGS__FRAMES_TXED_1519__COUNT__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_TXED_1519__TYPE                                         uint32_t
#define EMAC_REGS__FRAMES_TXED_1519__READ                                      0xffffffffU
#define EMAC_REGS__FRAMES_TXED_1519__RCLR                                      0xffffffffU

#endif /* __FRAMES_TXED_1519_MACRO__ */


/* macros for frames_txed_1519 */
#define EMAC_REGS__INST_FRAMES_TXED_1519__NUM                                            1

/* macros for BlueprintGlobalNameSpace::tx_underruns */
#ifndef __EMAC_REGS__TX_UNDERRUNS_MACRO__
#define __EMAC_REGS__TX_UNDERRUNS_MACRO__

/* macros for field count */
#define EMAC_REGS__TX_UNDERRUNS__COUNT__SHIFT                                            0
#define EMAC_REGS__TX_UNDERRUNS__COUNT__WIDTH                                           10
#define EMAC_REGS__TX_UNDERRUNS__COUNT__MASK                                   0x000003ffU
#define EMAC_REGS__TX_UNDERRUNS__COUNT__RESET                                            0
#define EMAC_REGS__TX_UNDERRUNS__COUNT__READ(src)          ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__TX_UNDERRUNS__RESERVED_31_10__SHIFT                                  10
#define EMAC_REGS__TX_UNDERRUNS__RESERVED_31_10__WIDTH                                  22
#define EMAC_REGS__TX_UNDERRUNS__RESERVED_31_10__MASK                          0xfffffc00U
#define EMAC_REGS__TX_UNDERRUNS__RESERVED_31_10__RESET                                   0
#define EMAC_REGS__TX_UNDERRUNS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__TX_UNDERRUNS__TYPE                                             uint32_t
#define EMAC_REGS__TX_UNDERRUNS__READ                                          0xffffffffU
#define EMAC_REGS__TX_UNDERRUNS__RCLR                                          0x000003ffU

#endif /* __TX_UNDERRUNS_MACRO__ */


/* macros for tx_underruns */
#define EMAC_REGS__INST_TX_UNDERRUNS__NUM                                                1

/* macros for BlueprintGlobalNameSpace::single_collisions */
#ifndef __EMAC_REGS__SINGLE_COLLISIONS_MACRO__
#define __EMAC_REGS__SINGLE_COLLISIONS_MACRO__

/* macros for field count */
#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__SHIFT                                       0
#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__WIDTH                                      18
#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__MASK                              0x0003ffffU
#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__RESET                                       0
#define EMAC_REGS__SINGLE_COLLISIONS__COUNT__READ(src)     ((uint32_t)(src) & 0x0003ffffU)

/* macros for field reserved_31_18 */
#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__SHIFT                             18
#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__WIDTH                             14
#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__MASK                     0xfffc0000U
#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__RESET                              0
#define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define EMAC_REGS__SINGLE_COLLISIONS__TYPE                                        uint32_t
#define EMAC_REGS__SINGLE_COLLISIONS__READ                                     0xffffffffU
#define EMAC_REGS__SINGLE_COLLISIONS__RCLR                                     0x0003ffffU

#endif /* __SINGLE_COLLISIONS_MACRO__ */


/* macros for single_collisions */
#define EMAC_REGS__INST_SINGLE_COLLISIONS__NUM                                           1

/* macros for BlueprintGlobalNameSpace::multiple_collisions */
#ifndef __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__
#define __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__

/* macros for field count */
#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__SHIFT                                     0
#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__WIDTH                                    18
#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__MASK                            0x0003ffffU
#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__RESET                                     0
#define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__READ(src)   ((uint32_t)(src) & 0x0003ffffU)

/* macros for field reserved_31_18 */
#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__SHIFT                           18
#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__WIDTH                           14
#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__MASK                   0xfffc0000U
#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__RESET                            0
#define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define EMAC_REGS__MULTIPLE_COLLISIONS__TYPE                                      uint32_t
#define EMAC_REGS__MULTIPLE_COLLISIONS__READ                                   0xffffffffU
#define EMAC_REGS__MULTIPLE_COLLISIONS__RCLR                                   0x0003ffffU

#endif /* __MULTIPLE_COLLISIONS_MACRO__ */


/* macros for multiple_collisions */
#define EMAC_REGS__INST_MULTIPLE_COLLISIONS__NUM                                         1

/* macros for BlueprintGlobalNameSpace::excessive_collisions */
#ifndef __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__
#define __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__

/* macros for field count */
#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__SHIFT                                    0
#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__WIDTH                                   10
#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__MASK                           0x000003ffU
#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__RESET                                    0
#define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__READ(src)  ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__SHIFT                          10
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__WIDTH                          22
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__MASK                  0xfffffc00U
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__RESET                           0
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__EXCESSIVE_COLLISIONS__TYPE                                     uint32_t
#define EMAC_REGS__EXCESSIVE_COLLISIONS__READ                                  0xffffffffU
#define EMAC_REGS__EXCESSIVE_COLLISIONS__RCLR                                  0x000003ffU

#endif /* __EXCESSIVE_COLLISIONS_MACRO__ */


/* macros for excessive_collisions */
#define EMAC_REGS__INST_EXCESSIVE_COLLISIONS__NUM                                        1

/* macros for BlueprintGlobalNameSpace::late_collisions */
#ifndef __EMAC_REGS__LATE_COLLISIONS_MACRO__
#define __EMAC_REGS__LATE_COLLISIONS_MACRO__

/* macros for field count */
#define EMAC_REGS__LATE_COLLISIONS__COUNT__SHIFT                                         0
#define EMAC_REGS__LATE_COLLISIONS__COUNT__WIDTH                                        10
#define EMAC_REGS__LATE_COLLISIONS__COUNT__MASK                                0x000003ffU
#define EMAC_REGS__LATE_COLLISIONS__COUNT__RESET                                         0
#define EMAC_REGS__LATE_COLLISIONS__COUNT__READ(src)       ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__SHIFT                               10
#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__WIDTH                               22
#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__MASK                       0xfffffc00U
#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__RESET                                0
#define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__LATE_COLLISIONS__TYPE                                          uint32_t
#define EMAC_REGS__LATE_COLLISIONS__READ                                       0xffffffffU
#define EMAC_REGS__LATE_COLLISIONS__RCLR                                       0x000003ffU

#endif /* __LATE_COLLISIONS_MACRO__ */


/* macros for late_collisions */
#define EMAC_REGS__INST_LATE_COLLISIONS__NUM                                             1

/* macros for BlueprintGlobalNameSpace::deferred_frames */
#ifndef __EMAC_REGS__DEFERRED_FRAMES_MACRO__
#define __EMAC_REGS__DEFERRED_FRAMES_MACRO__

/* macros for field count */
#define EMAC_REGS__DEFERRED_FRAMES__COUNT__SHIFT                                         0
#define EMAC_REGS__DEFERRED_FRAMES__COUNT__WIDTH                                        18
#define EMAC_REGS__DEFERRED_FRAMES__COUNT__MASK                                0x0003ffffU
#define EMAC_REGS__DEFERRED_FRAMES__COUNT__RESET                                         0
#define EMAC_REGS__DEFERRED_FRAMES__COUNT__READ(src)       ((uint32_t)(src) & 0x0003ffffU)

/* macros for field reserved_31_18 */
#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__SHIFT                               18
#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__WIDTH                               14
#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__MASK                       0xfffc0000U
#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__RESET                                0
#define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define EMAC_REGS__DEFERRED_FRAMES__TYPE                                          uint32_t
#define EMAC_REGS__DEFERRED_FRAMES__READ                                       0xffffffffU
#define EMAC_REGS__DEFERRED_FRAMES__RCLR                                       0x0003ffffU

#endif /* __DEFERRED_FRAMES_MACRO__ */


/* macros for deferred_frames */
#define EMAC_REGS__INST_DEFERRED_FRAMES__NUM                                             1

/* macros for BlueprintGlobalNameSpace::crs_errors */
#ifndef __EMAC_REGS__CRS_ERRORS_MACRO__
#define __EMAC_REGS__CRS_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__CRS_ERRORS__COUNT__SHIFT                                              0
#define EMAC_REGS__CRS_ERRORS__COUNT__WIDTH                                             10
#define EMAC_REGS__CRS_ERRORS__COUNT__MASK                                     0x000003ffU
#define EMAC_REGS__CRS_ERRORS__COUNT__RESET                                              0
#define EMAC_REGS__CRS_ERRORS__COUNT__READ(src)            ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__SHIFT                                    10
#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__WIDTH                                    22
#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__MASK                            0xfffffc00U
#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__RESET                                     0
#define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__CRS_ERRORS__TYPE                                               uint32_t
#define EMAC_REGS__CRS_ERRORS__READ                                            0xffffffffU
#define EMAC_REGS__CRS_ERRORS__RCLR                                            0x000003ffU

#endif /* __CRS_ERRORS_MACRO__ */


/* macros for crs_errors */
#define EMAC_REGS__INST_CRS_ERRORS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::octets_rxed_bottom */
#ifndef __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__
#define __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__

/* macros for field count */
#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__SHIFT                                      0
#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__WIDTH                                     32
#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__MASK                             0xffffffffU
#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__RESET                                      0
#define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__READ(src)    ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__OCTETS_RXED_BOTTOM__TYPE                                       uint32_t
#define EMAC_REGS__OCTETS_RXED_BOTTOM__READ                                    0xffffffffU
#define EMAC_REGS__OCTETS_RXED_BOTTOM__RCLR                                    0xffffffffU

#endif /* __OCTETS_RXED_BOTTOM_MACRO__ */


/* macros for octets_rxed_bottom */
#define EMAC_REGS__INST_OCTETS_RXED_BOTTOM__NUM                                          1

/* macros for BlueprintGlobalNameSpace::octets_rxed_top */
#ifndef __EMAC_REGS__OCTETS_RXED_TOP_MACRO__
#define __EMAC_REGS__OCTETS_RXED_TOP_MACRO__

/* macros for field count */
#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__SHIFT                                         0
#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__WIDTH                                        16
#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__MASK                                0x0000ffffU
#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__RESET                                         0
#define EMAC_REGS__OCTETS_RXED_TOP__COUNT__READ(src)       ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__SHIFT                               16
#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__WIDTH                               16
#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__MASK                       0xffff0000U
#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__RESET                                0
#define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__OCTETS_RXED_TOP__TYPE                                          uint32_t
#define EMAC_REGS__OCTETS_RXED_TOP__READ                                       0xffffffffU
#define EMAC_REGS__OCTETS_RXED_TOP__RCLR                                       0x0000ffffU

#endif /* __OCTETS_RXED_TOP_MACRO__ */


/* macros for octets_rxed_top */
#define EMAC_REGS__INST_OCTETS_RXED_TOP__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_rxed_ok */
#ifndef __EMAC_REGS__FRAMES_RXED_OK_MACRO__
#define __EMAC_REGS__FRAMES_RXED_OK_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_OK__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_RXED_OK__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_RXED_OK__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_RXED_OK__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_RXED_OK__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_OK__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_RXED_OK__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_RXED_OK__RCLR                                        0xffffffffU

#endif /* __FRAMES_RXED_OK_MACRO__ */


/* macros for frames_rxed_ok */
#define EMAC_REGS__INST_FRAMES_RXED_OK__NUM                                              1

/* macros for BlueprintGlobalNameSpace::broadcast_rxed */
#ifndef __EMAC_REGS__BROADCAST_RXED_MACRO__
#define __EMAC_REGS__BROADCAST_RXED_MACRO__

/* macros for field count */
#define EMAC_REGS__BROADCAST_RXED__COUNT__SHIFT                                          0
#define EMAC_REGS__BROADCAST_RXED__COUNT__WIDTH                                         32
#define EMAC_REGS__BROADCAST_RXED__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__BROADCAST_RXED__COUNT__RESET                                          0
#define EMAC_REGS__BROADCAST_RXED__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__BROADCAST_RXED__TYPE                                           uint32_t
#define EMAC_REGS__BROADCAST_RXED__READ                                        0xffffffffU
#define EMAC_REGS__BROADCAST_RXED__RCLR                                        0xffffffffU

#endif /* __BROADCAST_RXED_MACRO__ */


/* macros for broadcast_rxed */
#define EMAC_REGS__INST_BROADCAST_RXED__NUM                                              1

/* macros for BlueprintGlobalNameSpace::multicast_rxed */
#ifndef __EMAC_REGS__MULTICAST_RXED_MACRO__
#define __EMAC_REGS__MULTICAST_RXED_MACRO__

/* macros for field count */
#define EMAC_REGS__MULTICAST_RXED__COUNT__SHIFT                                          0
#define EMAC_REGS__MULTICAST_RXED__COUNT__WIDTH                                         32
#define EMAC_REGS__MULTICAST_RXED__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__MULTICAST_RXED__COUNT__RESET                                          0
#define EMAC_REGS__MULTICAST_RXED__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__MULTICAST_RXED__TYPE                                           uint32_t
#define EMAC_REGS__MULTICAST_RXED__READ                                        0xffffffffU
#define EMAC_REGS__MULTICAST_RXED__RCLR                                        0xffffffffU

#endif /* __MULTICAST_RXED_MACRO__ */


/* macros for multicast_rxed */
#define EMAC_REGS__INST_MULTICAST_RXED__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pause_frames_rxed */
#ifndef __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__
#define __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__

/* macros for field count */
#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__SHIFT                                       0
#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__WIDTH                                      16
#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__MASK                              0x0000ffffU
#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__RESET                                       0
#define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__READ(src)     ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__SHIFT                             16
#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__WIDTH                             16
#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__MASK                     0xffff0000U
#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__RESET                              0
#define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PAUSE_FRAMES_RXED__TYPE                                        uint32_t
#define EMAC_REGS__PAUSE_FRAMES_RXED__READ                                     0xffffffffU
#define EMAC_REGS__PAUSE_FRAMES_RXED__RCLR                                     0x0000ffffU

#endif /* __PAUSE_FRAMES_RXED_MACRO__ */


/* macros for pause_frames_rxed */
#define EMAC_REGS__INST_PAUSE_FRAMES_RXED__NUM                                           1

/* macros for BlueprintGlobalNameSpace::frames_rxed_64 */
#ifndef __EMAC_REGS__FRAMES_RXED_64_MACRO__
#define __EMAC_REGS__FRAMES_RXED_64_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_64__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_RXED_64__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_RXED_64__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_RXED_64__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_RXED_64__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_64__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_RXED_64__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_RXED_64__RCLR                                        0xffffffffU

#endif /* __FRAMES_RXED_64_MACRO__ */


/* macros for frames_rxed_64 */
#define EMAC_REGS__INST_FRAMES_RXED_64__NUM                                              1

/* macros for BlueprintGlobalNameSpace::frames_rxed_65 */
#ifndef __EMAC_REGS__FRAMES_RXED_65_MACRO__
#define __EMAC_REGS__FRAMES_RXED_65_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_65__COUNT__SHIFT                                          0
#define EMAC_REGS__FRAMES_RXED_65__COUNT__WIDTH                                         32
#define EMAC_REGS__FRAMES_RXED_65__COUNT__MASK                                 0xffffffffU
#define EMAC_REGS__FRAMES_RXED_65__COUNT__RESET                                          0
#define EMAC_REGS__FRAMES_RXED_65__COUNT__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_65__TYPE                                           uint32_t
#define EMAC_REGS__FRAMES_RXED_65__READ                                        0xffffffffU
#define EMAC_REGS__FRAMES_RXED_65__RCLR                                        0xffffffffU

#endif /* __FRAMES_RXED_65_MACRO__ */


/* macros for frames_rxed_65 */
#define EMAC_REGS__INST_FRAMES_RXED_65__NUM                                              1

/* macros for BlueprintGlobalNameSpace::frames_rxed_128 */
#ifndef __EMAC_REGS__FRAMES_RXED_128_MACRO__
#define __EMAC_REGS__FRAMES_RXED_128_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_128__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_RXED_128__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_RXED_128__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_RXED_128__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_RXED_128__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_128__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_RXED_128__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_RXED_128__RCLR                                       0xffffffffU

#endif /* __FRAMES_RXED_128_MACRO__ */


/* macros for frames_rxed_128 */
#define EMAC_REGS__INST_FRAMES_RXED_128__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_rxed_256 */
#ifndef __EMAC_REGS__FRAMES_RXED_256_MACRO__
#define __EMAC_REGS__FRAMES_RXED_256_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_256__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_RXED_256__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_RXED_256__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_RXED_256__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_RXED_256__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_256__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_RXED_256__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_RXED_256__RCLR                                       0xffffffffU

#endif /* __FRAMES_RXED_256_MACRO__ */


/* macros for frames_rxed_256 */
#define EMAC_REGS__INST_FRAMES_RXED_256__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_rxed_512 */
#ifndef __EMAC_REGS__FRAMES_RXED_512_MACRO__
#define __EMAC_REGS__FRAMES_RXED_512_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_512__COUNT__SHIFT                                         0
#define EMAC_REGS__FRAMES_RXED_512__COUNT__WIDTH                                        32
#define EMAC_REGS__FRAMES_RXED_512__COUNT__MASK                                0xffffffffU
#define EMAC_REGS__FRAMES_RXED_512__COUNT__RESET                                         0
#define EMAC_REGS__FRAMES_RXED_512__COUNT__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_512__TYPE                                          uint32_t
#define EMAC_REGS__FRAMES_RXED_512__READ                                       0xffffffffU
#define EMAC_REGS__FRAMES_RXED_512__RCLR                                       0xffffffffU

#endif /* __FRAMES_RXED_512_MACRO__ */


/* macros for frames_rxed_512 */
#define EMAC_REGS__INST_FRAMES_RXED_512__NUM                                             1

/* macros for BlueprintGlobalNameSpace::frames_rxed_1024 */
#ifndef __EMAC_REGS__FRAMES_RXED_1024_MACRO__
#define __EMAC_REGS__FRAMES_RXED_1024_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_1024__COUNT__SHIFT                                        0
#define EMAC_REGS__FRAMES_RXED_1024__COUNT__WIDTH                                       32
#define EMAC_REGS__FRAMES_RXED_1024__COUNT__MASK                               0xffffffffU
#define EMAC_REGS__FRAMES_RXED_1024__COUNT__RESET                                        0
#define EMAC_REGS__FRAMES_RXED_1024__COUNT__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_1024__TYPE                                         uint32_t
#define EMAC_REGS__FRAMES_RXED_1024__READ                                      0xffffffffU
#define EMAC_REGS__FRAMES_RXED_1024__RCLR                                      0xffffffffU

#endif /* __FRAMES_RXED_1024_MACRO__ */


/* macros for frames_rxed_1024 */
#define EMAC_REGS__INST_FRAMES_RXED_1024__NUM                                            1

/* macros for BlueprintGlobalNameSpace::frames_rxed_1519 */
#ifndef __EMAC_REGS__FRAMES_RXED_1519_MACRO__
#define __EMAC_REGS__FRAMES_RXED_1519_MACRO__

/* macros for field count */
#define EMAC_REGS__FRAMES_RXED_1519__COUNT__SHIFT                                        0
#define EMAC_REGS__FRAMES_RXED_1519__COUNT__WIDTH                                       32
#define EMAC_REGS__FRAMES_RXED_1519__COUNT__MASK                               0xffffffffU
#define EMAC_REGS__FRAMES_RXED_1519__COUNT__RESET                                        0
#define EMAC_REGS__FRAMES_RXED_1519__COUNT__READ(src)      ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__FRAMES_RXED_1519__TYPE                                         uint32_t
#define EMAC_REGS__FRAMES_RXED_1519__READ                                      0xffffffffU
#define EMAC_REGS__FRAMES_RXED_1519__RCLR                                      0xffffffffU

#endif /* __FRAMES_RXED_1519_MACRO__ */


/* macros for frames_rxed_1519 */
#define EMAC_REGS__INST_FRAMES_RXED_1519__NUM                                            1

/* macros for BlueprintGlobalNameSpace::undersize_frames */
#ifndef __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__
#define __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__

/* macros for field count */
#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__SHIFT                                        0
#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__WIDTH                                       10
#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__MASK                               0x000003ffU
#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__RESET                                        0
#define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__READ(src)      ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__SHIFT                              10
#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__WIDTH                              22
#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__MASK                      0xfffffc00U
#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__RESET                               0
#define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__UNDERSIZE_FRAMES__TYPE                                         uint32_t
#define EMAC_REGS__UNDERSIZE_FRAMES__READ                                      0xffffffffU
#define EMAC_REGS__UNDERSIZE_FRAMES__RCLR                                      0x000003ffU

#endif /* __UNDERSIZE_FRAMES_MACRO__ */


/* macros for undersize_frames */
#define EMAC_REGS__INST_UNDERSIZE_FRAMES__NUM                                            1

/* macros for BlueprintGlobalNameSpace::excessive_rx_length */
#ifndef __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__
#define __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__

/* macros for field count */
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__SHIFT                                     0
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__WIDTH                                    10
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__MASK                            0x000003ffU
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__RESET                                     0
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__READ(src)   ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__SHIFT                           10
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__WIDTH                           22
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__MASK                   0xfffffc00U
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__RESET                            0
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__TYPE                                      uint32_t
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__READ                                   0xffffffffU
#define EMAC_REGS__EXCESSIVE_RX_LENGTH__RCLR                                   0x000003ffU

#endif /* __EXCESSIVE_RX_LENGTH_MACRO__ */


/* macros for excessive_rx_length */
#define EMAC_REGS__INST_EXCESSIVE_RX_LENGTH__NUM                                         1

/* macros for BlueprintGlobalNameSpace::rx_jabbers */
#ifndef __EMAC_REGS__RX_JABBERS_MACRO__
#define __EMAC_REGS__RX_JABBERS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_JABBERS__COUNT__SHIFT                                              0
#define EMAC_REGS__RX_JABBERS__COUNT__WIDTH                                             10
#define EMAC_REGS__RX_JABBERS__COUNT__MASK                                     0x000003ffU
#define EMAC_REGS__RX_JABBERS__COUNT__RESET                                              0
#define EMAC_REGS__RX_JABBERS__COUNT__READ(src)            ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__SHIFT                                    10
#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__WIDTH                                    22
#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__MASK                            0xfffffc00U
#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__RESET                                     0
#define EMAC_REGS__RX_JABBERS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__RX_JABBERS__TYPE                                               uint32_t
#define EMAC_REGS__RX_JABBERS__READ                                            0xffffffffU
#define EMAC_REGS__RX_JABBERS__RCLR                                            0x000003ffU

#endif /* __RX_JABBERS_MACRO__ */


/* macros for rx_jabbers */
#define EMAC_REGS__INST_RX_JABBERS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::fcs_errors */
#ifndef __EMAC_REGS__FCS_ERRORS_MACRO__
#define __EMAC_REGS__FCS_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__FCS_ERRORS__COUNT__SHIFT                                              0
#define EMAC_REGS__FCS_ERRORS__COUNT__WIDTH                                             10
#define EMAC_REGS__FCS_ERRORS__COUNT__MASK                                     0x000003ffU
#define EMAC_REGS__FCS_ERRORS__COUNT__RESET                                              0
#define EMAC_REGS__FCS_ERRORS__COUNT__READ(src)            ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__SHIFT                                    10
#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__WIDTH                                    22
#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__MASK                            0xfffffc00U
#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__RESET                                     0
#define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__FCS_ERRORS__TYPE                                               uint32_t
#define EMAC_REGS__FCS_ERRORS__READ                                            0xffffffffU
#define EMAC_REGS__FCS_ERRORS__RCLR                                            0x000003ffU

#endif /* __FCS_ERRORS_MACRO__ */


/* macros for fcs_errors */
#define EMAC_REGS__INST_FCS_ERRORS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::rx_length_errors */
#ifndef __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__
#define __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__SHIFT                                        0
#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__WIDTH                                       10
#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__MASK                               0x000003ffU
#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__RESET                                        0
#define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__READ(src)      ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__SHIFT                              10
#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__WIDTH                              22
#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__MASK                      0xfffffc00U
#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__RESET                               0
#define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__RX_LENGTH_ERRORS__TYPE                                         uint32_t
#define EMAC_REGS__RX_LENGTH_ERRORS__READ                                      0xffffffffU
#define EMAC_REGS__RX_LENGTH_ERRORS__RCLR                                      0x000003ffU

#endif /* __RX_LENGTH_ERRORS_MACRO__ */


/* macros for rx_length_errors */
#define EMAC_REGS__INST_RX_LENGTH_ERRORS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::rx_symbol_errors */
#ifndef __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__
#define __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__SHIFT                                        0
#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__WIDTH                                       10
#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__MASK                               0x000003ffU
#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__RESET                                        0
#define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__READ(src)      ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__SHIFT                              10
#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__WIDTH                              22
#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__MASK                      0xfffffc00U
#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__RESET                               0
#define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__RX_SYMBOL_ERRORS__TYPE                                         uint32_t
#define EMAC_REGS__RX_SYMBOL_ERRORS__READ                                      0xffffffffU
#define EMAC_REGS__RX_SYMBOL_ERRORS__RCLR                                      0x000003ffU

#endif /* __RX_SYMBOL_ERRORS_MACRO__ */


/* macros for rx_symbol_errors */
#define EMAC_REGS__INST_RX_SYMBOL_ERRORS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::alignment_errors */
#ifndef __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__
#define __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__SHIFT                                        0
#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__WIDTH                                       10
#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__MASK                               0x000003ffU
#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__RESET                                        0
#define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__READ(src)      ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__SHIFT                              10
#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__WIDTH                              22
#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__MASK                      0xfffffc00U
#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__RESET                               0
#define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__ALIGNMENT_ERRORS__TYPE                                         uint32_t
#define EMAC_REGS__ALIGNMENT_ERRORS__READ                                      0xffffffffU
#define EMAC_REGS__ALIGNMENT_ERRORS__RCLR                                      0x000003ffU

#endif /* __ALIGNMENT_ERRORS_MACRO__ */


/* macros for alignment_errors */
#define EMAC_REGS__INST_ALIGNMENT_ERRORS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::rx_resource_errors */
#ifndef __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__
#define __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__SHIFT                                      0
#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__WIDTH                                     18
#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__MASK                             0x0003ffffU
#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__RESET                                      0
#define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__READ(src)    ((uint32_t)(src) & 0x0003ffffU)

/* macros for field reserved_31_18 */
#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__SHIFT                            18
#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__WIDTH                            14
#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__MASK                    0xfffc0000U
#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__RESET                             0
#define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define EMAC_REGS__RX_RESOURCE_ERRORS__TYPE                                       uint32_t
#define EMAC_REGS__RX_RESOURCE_ERRORS__READ                                    0xffffffffU
#define EMAC_REGS__RX_RESOURCE_ERRORS__RCLR                                    0x0003ffffU

#endif /* __RX_RESOURCE_ERRORS_MACRO__ */


/* macros for rx_resource_errors */
#define EMAC_REGS__INST_RX_RESOURCE_ERRORS__NUM                                          1

/* macros for BlueprintGlobalNameSpace::rx_overruns */
#ifndef __EMAC_REGS__RX_OVERRUNS_MACRO__
#define __EMAC_REGS__RX_OVERRUNS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_OVERRUNS__COUNT__SHIFT                                             0
#define EMAC_REGS__RX_OVERRUNS__COUNT__WIDTH                                            10
#define EMAC_REGS__RX_OVERRUNS__COUNT__MASK                                    0x000003ffU
#define EMAC_REGS__RX_OVERRUNS__COUNT__RESET                                             0
#define EMAC_REGS__RX_OVERRUNS__COUNT__READ(src)           ((uint32_t)(src) & 0x000003ffU)

/* macros for field reserved_31_10 */
#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__SHIFT                                   10
#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__WIDTH                                   22
#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__MASK                           0xfffffc00U
#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__RESET                                    0
#define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffc00U) >> 10)
#define EMAC_REGS__RX_OVERRUNS__TYPE                                              uint32_t
#define EMAC_REGS__RX_OVERRUNS__READ                                           0xffffffffU
#define EMAC_REGS__RX_OVERRUNS__RCLR                                           0x000003ffU

#endif /* __RX_OVERRUNS_MACRO__ */


/* macros for rx_overruns */
#define EMAC_REGS__INST_RX_OVERRUNS__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::rx_ip_ck_errors */
#ifndef __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__
#define __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__SHIFT                                         0
#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__WIDTH                                         8
#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__MASK                                0x000000ffU
#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__RESET                                         0
#define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__READ(src)       ((uint32_t)(src) & 0x000000ffU)

/* macros for field reserved_31_8 */
#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__SHIFT                                 8
#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__WIDTH                                24
#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__MASK                        0xffffff00U
#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__RESET                                 0
#define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__RX_IP_CK_ERRORS__TYPE                                          uint32_t
#define EMAC_REGS__RX_IP_CK_ERRORS__READ                                       0xffffffffU
#define EMAC_REGS__RX_IP_CK_ERRORS__RCLR                                       0x000000ffU

#endif /* __RX_IP_CK_ERRORS_MACRO__ */


/* macros for rx_ip_ck_errors */
#define EMAC_REGS__INST_RX_IP_CK_ERRORS__NUM                                             1

/* macros for BlueprintGlobalNameSpace::rx_tcp_ck_errors */
#ifndef __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__
#define __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__SHIFT                                        0
#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__WIDTH                                        8
#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__MASK                               0x000000ffU
#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__RESET                                        0
#define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__READ(src)      ((uint32_t)(src) & 0x000000ffU)

/* macros for field reserved_31_8 */
#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__SHIFT                                8
#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__WIDTH                               24
#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__MASK                       0xffffff00U
#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__RESET                                0
#define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__RX_TCP_CK_ERRORS__TYPE                                         uint32_t
#define EMAC_REGS__RX_TCP_CK_ERRORS__READ                                      0xffffffffU
#define EMAC_REGS__RX_TCP_CK_ERRORS__RCLR                                      0x000000ffU

#endif /* __RX_TCP_CK_ERRORS_MACRO__ */


/* macros for rx_tcp_ck_errors */
#define EMAC_REGS__INST_RX_TCP_CK_ERRORS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::rx_udp_ck_errors */
#ifndef __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__
#define __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__SHIFT                                        0
#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__WIDTH                                        8
#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__MASK                               0x000000ffU
#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__RESET                                        0
#define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__READ(src)      ((uint32_t)(src) & 0x000000ffU)

/* macros for field reserved_31_8 */
#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__SHIFT                                8
#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__WIDTH                               24
#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__MASK                       0xffffff00U
#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__RESET                                0
#define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__RX_UDP_CK_ERRORS__TYPE                                         uint32_t
#define EMAC_REGS__RX_UDP_CK_ERRORS__READ                                      0xffffffffU
#define EMAC_REGS__RX_UDP_CK_ERRORS__RCLR                                      0x000000ffU

#endif /* __RX_UDP_CK_ERRORS_MACRO__ */


/* macros for rx_udp_ck_errors */
#define EMAC_REGS__INST_RX_UDP_CK_ERRORS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::auto_flushed_pkts */
#ifndef __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__
#define __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__

/* macros for field count */
#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__SHIFT                                       0
#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__WIDTH                                      16
#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__MASK                              0x0000ffffU
#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__RESET                                       0
#define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__READ(src)     ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__SHIFT                             16
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__WIDTH                             16
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__MASK                     0xffff0000U
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__RESET                              0
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__AUTO_FLUSHED_PKTS__TYPE                                        uint32_t
#define EMAC_REGS__AUTO_FLUSHED_PKTS__READ                                     0xffffffffU
#define EMAC_REGS__AUTO_FLUSHED_PKTS__RCLR                                     0x0000ffffU

#endif /* __AUTO_FLUSHED_PKTS_MACRO__ */


/* macros for auto_flushed_pkts */
#define EMAC_REGS__INST_AUTO_FLUSHED_PKTS__NUM                                           1

/* macros for BlueprintGlobalNameSpace::tsu_timer_incr_sub_nsec */
#ifndef __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__
#define __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__

/* macros for field sub_ns_incr */
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__SHIFT                           0
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WIDTH                          16
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MASK                  0x0000ffffU
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__RESET                           0
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_23_16 */
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__SHIFT                       16
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__WIDTH                        8
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__MASK               0x00ff0000U
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__RESET                        0
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field sub_ns_incr_lsb */
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__SHIFT                      24
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WIDTH                       8
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MASK              0xff000000U
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__RESET                       0
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__TYPE                                  uint32_t
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__READ                               0xffffffffU
#define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__WRITE                              0xffffffffU

#endif /* __TSU_TIMER_INCR_SUB_NSEC_MACRO__ */


/* macros for tsu_timer_incr_sub_nsec */
#define EMAC_REGS__INST_TSU_TIMER_INCR_SUB_NSEC__NUM                                     1

/* macros for BlueprintGlobalNameSpace::tsu_timer_msb_sec */
#ifndef __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__SHIFT                                       0
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WIDTH                                      16
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MASK                              0x0000ffffU
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__RESET                                       0
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__READ(src)     ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WRITE(src)    ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__SHIFT                             16
#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__WIDTH                             16
#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__MASK                     0xffff0000U
#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__RESET                              0
#define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_TIMER_MSB_SEC__TYPE                                        uint32_t
#define EMAC_REGS__TSU_TIMER_MSB_SEC__READ                                     0xffffffffU
#define EMAC_REGS__TSU_TIMER_MSB_SEC__WRITE                                    0xffffffffU

#endif /* __TSU_TIMER_MSB_SEC_MACRO__ */


/* macros for tsu_timer_msb_sec */
#define EMAC_REGS__INST_TSU_TIMER_MSB_SEC__NUM                                           1

/* macros for BlueprintGlobalNameSpace::tsu_strobe_msb_sec */
#ifndef __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__
#define __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__

/* macros for field strobe */
#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__SHIFT                                     0
#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__WIDTH                                    16
#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__MASK                            0x0000ffffU
#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__RESET                                     0
#define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__READ(src)   ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__SHIFT                            16
#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__WIDTH                            16
#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__MASK                    0xffff0000U
#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__RESET                             0
#define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TSU_STROBE_MSB_SEC__TYPE                                       uint32_t
#define EMAC_REGS__TSU_STROBE_MSB_SEC__READ                                    0xffffffffU

#endif /* __TSU_STROBE_MSB_SEC_MACRO__ */


/* macros for tsu_strobe_msb_sec */
#define EMAC_REGS__INST_TSU_STROBE_MSB_SEC__NUM                                          1

/* macros for BlueprintGlobalNameSpace::tsu_strobe_sec */
#ifndef __EMAC_REGS__TSU_STROBE_SEC_MACRO__
#define __EMAC_REGS__TSU_STROBE_SEC_MACRO__

/* macros for field strobe */
#define EMAC_REGS__TSU_STROBE_SEC__STROBE__SHIFT                                         0
#define EMAC_REGS__TSU_STROBE_SEC__STROBE__WIDTH                                        32
#define EMAC_REGS__TSU_STROBE_SEC__STROBE__MASK                                0xffffffffU
#define EMAC_REGS__TSU_STROBE_SEC__STROBE__RESET                                         0
#define EMAC_REGS__TSU_STROBE_SEC__STROBE__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_STROBE_SEC__TYPE                                           uint32_t
#define EMAC_REGS__TSU_STROBE_SEC__READ                                        0xffffffffU

#endif /* __TSU_STROBE_SEC_MACRO__ */


/* macros for tsu_strobe_sec */
#define EMAC_REGS__INST_TSU_STROBE_SEC__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_strobe_nsec */
#ifndef __EMAC_REGS__TSU_STROBE_NSEC_MACRO__
#define __EMAC_REGS__TSU_STROBE_NSEC_MACRO__

/* macros for field strobe */
#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__SHIFT                                        0
#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__WIDTH                                       30
#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__MASK                               0x3fffffffU
#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__RESET                                        0
#define EMAC_REGS__TSU_STROBE_NSEC__STROBE__READ(src)      ((uint32_t)(src) & 0x3fffffffU)

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__SHIFT                               30
#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__WIDTH                                2
#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__MASK                       0xc0000000U
#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__RESET                                0
#define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_STROBE_NSEC__TYPE                                          uint32_t
#define EMAC_REGS__TSU_STROBE_NSEC__READ                                       0xffffffffU

#endif /* __TSU_STROBE_NSEC_MACRO__ */


/* macros for tsu_strobe_nsec */
#define EMAC_REGS__INST_TSU_STROBE_NSEC__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_timer_sec */
#ifndef __EMAC_REGS__TSU_TIMER_SEC_MACRO__
#define __EMAC_REGS__TSU_TIMER_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__SHIFT                                           0
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__WIDTH                                          32
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__MASK                                  0xffffffffU
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__RESET                                           0
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__READ(src)         ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__WRITE(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__TSU_TIMER_SEC__TIMER__VERIFY(src) (!(((uint32_t)(src) & ~0xffffffffU)))
#define EMAC_REGS__TSU_TIMER_SEC__TYPE                                            uint32_t
#define EMAC_REGS__TSU_TIMER_SEC__READ                                         0xffffffffU
#define EMAC_REGS__TSU_TIMER_SEC__WRITE                                        0xffffffffU

#endif /* __TSU_TIMER_SEC_MACRO__ */


/* macros for tsu_timer_sec */
#define EMAC_REGS__INST_TSU_TIMER_SEC__NUM                                               1

/* macros for BlueprintGlobalNameSpace::tsu_timer_nsec */
#ifndef __EMAC_REGS__TSU_TIMER_NSEC_MACRO__
#define __EMAC_REGS__TSU_TIMER_NSEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__SHIFT                                          0
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WIDTH                                         30
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MASK                                 0x3fffffffU
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__RESET                                          0
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ(src)        ((uint32_t)(src) & 0x3fffffffU)
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WRITE(src)       ((uint32_t)(src) & 0x3fffffffU)
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__TSU_TIMER_NSEC__TIMER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__SHIFT                                30
#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__WIDTH                                 2
#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__MASK                        0xc0000000U
#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__RESET                                 0
#define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_TIMER_NSEC__TYPE                                           uint32_t
#define EMAC_REGS__TSU_TIMER_NSEC__READ                                        0xffffffffU
#define EMAC_REGS__TSU_TIMER_NSEC__WRITE                                       0xffffffffU

#endif /* __TSU_TIMER_NSEC_MACRO__ */


/* macros for tsu_timer_nsec */
#define EMAC_REGS__INST_TSU_TIMER_NSEC__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_timer_adjust */
#ifndef __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__
#define __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__

/* macros for field increment_value */
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__SHIFT                              0
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WIDTH                             30
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MASK                     0x3fffffffU
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__RESET                              0
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field reserved_30 */
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__SHIFT                                 30
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__WIDTH                                  1
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__MASK                         0x40000000U
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__RESET                                  0
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field add_subtract */
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SHIFT                                31
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WIDTH                                 1
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MASK                        0x80000000U
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__RESET                                 0
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__TSU_TIMER_ADJUST__TYPE                                         uint32_t
#define EMAC_REGS__TSU_TIMER_ADJUST__READ                                      0x40000000U
#define EMAC_REGS__TSU_TIMER_ADJUST__WRITE                                     0x40000000U

#endif /* __TSU_TIMER_ADJUST_MACRO__ */


/* macros for tsu_timer_adjust */
#define EMAC_REGS__INST_TSU_TIMER_ADJUST__NUM                                            1

/* macros for BlueprintGlobalNameSpace::tsu_timer_incr */
#ifndef __EMAC_REGS__TSU_TIMER_INCR_MACRO__
#define __EMAC_REGS__TSU_TIMER_INCR_MACRO__

/* macros for field ns_increment */
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__SHIFT                                   0
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WIDTH                                   8
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MASK                          0x000000ffU
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__RESET                                   0
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__READ(src) ((uint32_t)(src) & 0x000000ffU)
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field alt_ns_incr */
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__SHIFT                                    8
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WIDTH                                    8
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MASK                           0x0000ff00U
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__RESET                                    0
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field num_incs */
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__SHIFT                                      16
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WIDTH                                       8
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MASK                              0x00ff0000U
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__RESET                                       0
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field reserved_31_24 */
#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__SHIFT                                24
#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__WIDTH                                 8
#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__MASK                        0xff000000U
#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__RESET                                 0
#define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__TSU_TIMER_INCR__TYPE                                           uint32_t
#define EMAC_REGS__TSU_TIMER_INCR__READ                                        0xffffffffU
#define EMAC_REGS__TSU_TIMER_INCR__WRITE                                       0xffffffffU

#endif /* __TSU_TIMER_INCR_MACRO__ */


/* macros for tsu_timer_incr */
#define EMAC_REGS__INST_TSU_TIMER_INCR__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_tx_sec */
#ifndef __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__
#define __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__SHIFT                                          0
#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__WIDTH                                         32
#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__MASK                                 0xffffffffU
#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__RESET                                          0
#define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_PTP_TX_SEC__TYPE                                           uint32_t
#define EMAC_REGS__TSU_PTP_TX_SEC__READ                                        0xffffffffU

#endif /* __TSU_PTP_TX_SEC_MACRO__ */


/* macros for tsu_ptp_tx_sec */
#define EMAC_REGS__INST_TSU_PTP_TX_SEC__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_tx_nsec */
#ifndef __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__
#define __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__SHIFT                                         0
#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__WIDTH                                        30
#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__MASK                                0x3fffffffU
#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__RESET                                         0
#define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__READ(src)       ((uint32_t)(src) & 0x3fffffffU)

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__SHIFT                               30
#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__WIDTH                                2
#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__MASK                       0xc0000000U
#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__RESET                                0
#define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_PTP_TX_NSEC__TYPE                                          uint32_t
#define EMAC_REGS__TSU_PTP_TX_NSEC__READ                                       0xffffffffU

#endif /* __TSU_PTP_TX_NSEC_MACRO__ */


/* macros for tsu_ptp_tx_nsec */
#define EMAC_REGS__INST_TSU_PTP_TX_NSEC__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_rx_sec */
#ifndef __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__
#define __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__SHIFT                                          0
#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__WIDTH                                         32
#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__MASK                                 0xffffffffU
#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__RESET                                          0
#define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__READ(src)        ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_PTP_RX_SEC__TYPE                                           uint32_t
#define EMAC_REGS__TSU_PTP_RX_SEC__READ                                        0xffffffffU

#endif /* __TSU_PTP_RX_SEC_MACRO__ */


/* macros for tsu_ptp_rx_sec */
#define EMAC_REGS__INST_TSU_PTP_RX_SEC__NUM                                              1

/* macros for BlueprintGlobalNameSpace::tsu_ptp_rx_nsec */
#ifndef __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__
#define __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__SHIFT                                         0
#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__WIDTH                                        30
#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__MASK                                0x3fffffffU
#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__RESET                                         0
#define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__READ(src)       ((uint32_t)(src) & 0x3fffffffU)

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__SHIFT                               30
#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__WIDTH                                2
#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__MASK                       0xc0000000U
#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__RESET                                0
#define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_PTP_RX_NSEC__TYPE                                          uint32_t
#define EMAC_REGS__TSU_PTP_RX_NSEC__READ                                       0xffffffffU

#endif /* __TSU_PTP_RX_NSEC_MACRO__ */


/* macros for tsu_ptp_rx_nsec */
#define EMAC_REGS__INST_TSU_PTP_RX_NSEC__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_peer_tx_sec */
#ifndef __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__
#define __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__SHIFT                                         0
#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__WIDTH                                        32
#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__MASK                                0xffffffffU
#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__RESET                                         0
#define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_PEER_TX_SEC__TYPE                                          uint32_t
#define EMAC_REGS__TSU_PEER_TX_SEC__READ                                       0xffffffffU

#endif /* __TSU_PEER_TX_SEC_MACRO__ */


/* macros for tsu_peer_tx_sec */
#define EMAC_REGS__INST_TSU_PEER_TX_SEC__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_peer_tx_nsec */
#ifndef __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__
#define __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__SHIFT                                        0
#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__WIDTH                                       30
#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__MASK                               0x3fffffffU
#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__RESET                                        0
#define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__READ(src)      ((uint32_t)(src) & 0x3fffffffU)

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__SHIFT                              30
#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__WIDTH                               2
#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__MASK                      0xc0000000U
#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__RESET                               0
#define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_PEER_TX_NSEC__TYPE                                         uint32_t
#define EMAC_REGS__TSU_PEER_TX_NSEC__READ                                      0xffffffffU

#endif /* __TSU_PEER_TX_NSEC_MACRO__ */


/* macros for tsu_peer_tx_nsec */
#define EMAC_REGS__INST_TSU_PEER_TX_NSEC__NUM                                            1

/* macros for BlueprintGlobalNameSpace::tsu_peer_rx_sec */
#ifndef __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__
#define __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__SHIFT                                         0
#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__WIDTH                                        32
#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__MASK                                0xffffffffU
#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__RESET                                         0
#define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__READ(src)       ((uint32_t)(src) & 0xffffffffU)
#define EMAC_REGS__TSU_PEER_RX_SEC__TYPE                                          uint32_t
#define EMAC_REGS__TSU_PEER_RX_SEC__READ                                       0xffffffffU

#endif /* __TSU_PEER_RX_SEC_MACRO__ */


/* macros for tsu_peer_rx_sec */
#define EMAC_REGS__INST_TSU_PEER_RX_SEC__NUM                                             1

/* macros for BlueprintGlobalNameSpace::tsu_peer_rx_nsec */
#ifndef __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__
#define __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__

/* macros for field timer */
#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__SHIFT                                        0
#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__WIDTH                                       30
#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__MASK                               0x3fffffffU
#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__RESET                                        0
#define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__READ(src)      ((uint32_t)(src) & 0x3fffffffU)

/* macros for field reserved_31_30 */
#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__SHIFT                              30
#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__WIDTH                               2
#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__MASK                      0xc0000000U
#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__RESET                               0
#define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TSU_PEER_RX_NSEC__TYPE                                         uint32_t
#define EMAC_REGS__TSU_PEER_RX_NSEC__READ                                      0xffffffffU

#endif /* __TSU_PEER_RX_NSEC_MACRO__ */


/* macros for tsu_peer_rx_nsec */
#define EMAC_REGS__INST_TSU_PEER_RX_NSEC__NUM                                            1

/* macros for BlueprintGlobalNameSpace::pcs_control */
#ifndef __EMAC_REGS__PCS_CONTROL_MACRO__
#define __EMAC_REGS__PCS_CONTROL_MACRO__

/* macros for field reserved_5_0 */
#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__SHIFT                                      0
#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__WIDTH                                      6
#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__MASK                             0x0000003fU
#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__RESET                                      0
#define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__READ(src)    ((uint32_t)(src) & 0x0000003fU)

/* macros for field speed_select_bit_0 */
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SHIFT                                6
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__WIDTH                                1
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__MASK                       0x00000040U
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__RESET                                1
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field collision_test */
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SHIFT                                    7
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WIDTH                                    1
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MASK                           0x00000080U
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__RESET                                    0
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field mac_duplex_state */
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SHIFT                                  8
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__WIDTH                                  1
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__MASK                         0x00000100U
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__RESET                                  0
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field restart_auto_neg */
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SHIFT                                  9
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WIDTH                                  1
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MASK                         0x00000200U
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__RESET                                  0
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field reserved_11_10 */
#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__SHIFT                                   10
#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__WIDTH                                    2
#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__MASK                           0x00000c00U
#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__RESET                                    0
#define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000c00U) >> 10)

/* macros for field enable_auto_neg */
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SHIFT                                  12
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WIDTH                                   1
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MASK                          0x00001000U
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__RESET                                   1
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field speed_select_bit_1 */
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SHIFT                               13
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__WIDTH                                1
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__MASK                       0x00002000U
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__RESET                                0
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field loopback_mode */
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SHIFT                                    14
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WIDTH                                     1
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MASK                            0x00004000U
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__RESET                                     0
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field pcs_software_reset */
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SHIFT                               15
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WIDTH                                1
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MASK                       0x00008000U
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__RESET                                1
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__SHIFT                                   16
#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__WIDTH                                   16
#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__MASK                           0xffff0000U
#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__RESET                                    0
#define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_CONTROL__TYPE                                              uint32_t
#define EMAC_REGS__PCS_CONTROL__READ                                           0xffffffffU
#define EMAC_REGS__PCS_CONTROL__WRITE                                          0xffffffffU

#endif /* __PCS_CONTROL_MACRO__ */


/* macros for pcs_control */
#define EMAC_REGS__INST_PCS_CONTROL__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::pcs_status */
#ifndef __EMAC_REGS__PCS_STATUS_MACRO__
#define __EMAC_REGS__PCS_STATUS_MACRO__

/* macros for field extended_capabilities */
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SHIFT                              0
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__WIDTH                              1
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__MASK                     0x00000001U
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__RESET                              1
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_1 */
#define EMAC_REGS__PCS_STATUS__RESERVED_1__SHIFT                                         1
#define EMAC_REGS__PCS_STATUS__RESERVED_1__WIDTH                                         1
#define EMAC_REGS__PCS_STATUS__RESERVED_1__MASK                                0x00000002U
#define EMAC_REGS__PCS_STATUS__RESERVED_1__RESET                                         0
#define EMAC_REGS__PCS_STATUS__RESERVED_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__PCS_STATUS__RESERVED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__PCS_STATUS__RESERVED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field link_status */
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__SHIFT                                        2
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__WIDTH                                        1
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__MASK                               0x00000004U
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__RESET                                        0
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__PCS_STATUS__LINK_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field auto_neg_ability */
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SHIFT                                   3
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__WIDTH                                   1
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__MASK                          0x00000008U
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__RESET                                   1
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field remote_fault */
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SHIFT                                       4
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__WIDTH                                       1
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__MASK                              0x00000010U
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__RESET                                       0
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field auto_neg_complete */
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SHIFT                                  5
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__WIDTH                                  1
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__MASK                         0x00000020U
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__RESET                                  0
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_7_6 */
#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__SHIFT                                       6
#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__WIDTH                                       2
#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__MASK                              0x000000c0U
#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__RESET                                       0
#define EMAC_REGS__PCS_STATUS__RESERVED_7_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000c0U) >> 6)

/* macros for field extended_status */
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SHIFT                                    8
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__WIDTH                                    1
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__MASK                           0x00000100U
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__RESET                                    1
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field base_100_t2_half_duplex */
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SHIFT                            9
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__WIDTH                            1
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__MASK                   0x00000200U
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__RESET                            0
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field base_100_t2_full_duplex */
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SHIFT                           10
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__WIDTH                            1
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__MASK                   0x00000400U
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__RESET                            0
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field mbps_10_half_duplex */
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SHIFT                               11
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__WIDTH                                1
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__MASK                       0x00000800U
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__RESET                                0
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field mbps_10_full_duplex */
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SHIFT                               12
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__WIDTH                                1
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__MASK                       0x00001000U
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__RESET                                0
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field base_100_x_half_duplex */
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SHIFT                            13
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__WIDTH                             1
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__MASK                    0x00002000U
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__RESET                             0
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field base_100_x_full_duplex */
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SHIFT                            14
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__WIDTH                             1
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__MASK                    0x00004000U
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__RESET                             0
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field base_100_t4 */
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__SHIFT                                       15
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__WIDTH                                        1
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__MASK                               0x00008000U
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__RESET                                        0
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_STATUS__BASE_100_T4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__SHIFT                                    16
#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__WIDTH                                    16
#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__MASK                            0xffff0000U
#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__RESET                                     0
#define EMAC_REGS__PCS_STATUS__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_STATUS__TYPE                                               uint32_t
#define EMAC_REGS__PCS_STATUS__READ                                            0xffffffffU

#endif /* __PCS_STATUS_MACRO__ */


/* macros for pcs_status */
#define EMAC_REGS__INST_PCS_STATUS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::pcs_phy_top_id */
#ifndef __EMAC_REGS__PCS_PHY_TOP_ID_MACRO__
#define __EMAC_REGS__PCS_PHY_TOP_ID_MACRO__

/* macros for field id_code */
#define EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__SHIFT                                        0
#define EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__WIDTH                                       16
#define EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__MASK                               0x0000ffffU
#define EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__RESET                                        7
#define EMAC_REGS__PCS_PHY_TOP_ID__ID_CODE__READ(src)      ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_PHY_TOP_ID__RESERVED_31_16__SHIFT                                16
#define EMAC_REGS__PCS_PHY_TOP_ID__RESERVED_31_16__WIDTH                                16
#define EMAC_REGS__PCS_PHY_TOP_ID__RESERVED_31_16__MASK                        0xffff0000U
#define EMAC_REGS__PCS_PHY_TOP_ID__RESERVED_31_16__RESET                                 0
#define EMAC_REGS__PCS_PHY_TOP_ID__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_PHY_TOP_ID__TYPE                                           uint32_t
#define EMAC_REGS__PCS_PHY_TOP_ID__READ                                        0xffffffffU

#endif /* __PCS_PHY_TOP_ID_MACRO__ */


/* macros for pcs_phy_top_id */
#define EMAC_REGS__INST_PCS_PHY_TOP_ID__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pcs_phy_bot_id */
#ifndef __EMAC_REGS__PCS_PHY_BOT_ID_MACRO__
#define __EMAC_REGS__PCS_PHY_BOT_ID_MACRO__

/* macros for field id_code */
#define EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__SHIFT                                        0
#define EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__WIDTH                                       16
#define EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__MASK                               0x0000ffffU
#define EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__RESET                                      512
#define EMAC_REGS__PCS_PHY_BOT_ID__ID_CODE__READ(src)      ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_PHY_BOT_ID__RESERVED_31_16__SHIFT                                16
#define EMAC_REGS__PCS_PHY_BOT_ID__RESERVED_31_16__WIDTH                                16
#define EMAC_REGS__PCS_PHY_BOT_ID__RESERVED_31_16__MASK                        0xffff0000U
#define EMAC_REGS__PCS_PHY_BOT_ID__RESERVED_31_16__RESET                                 0
#define EMAC_REGS__PCS_PHY_BOT_ID__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_PHY_BOT_ID__TYPE                                           uint32_t
#define EMAC_REGS__PCS_PHY_BOT_ID__READ                                        0xffffffffU

#endif /* __PCS_PHY_BOT_ID_MACRO__ */


/* macros for pcs_phy_bot_id */
#define EMAC_REGS__INST_PCS_PHY_BOT_ID__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pcs_an_adv */
#ifndef __EMAC_REGS__PCS_AN_ADV_MACRO__
#define __EMAC_REGS__PCS_AN_ADV_MACRO__

/* macros for field reserved_4_0 */
#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__SHIFT                                       0
#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__WIDTH                                       5
#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__MASK                              0x0000001fU
#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__RESET                                       0
#define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__READ(src)     ((uint32_t)(src) & 0x0000001fU)

/* macros for field full_duplex */
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SHIFT                                        5
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WIDTH                                        1
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MASK                               0x00000020U
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__RESET                                        1
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field half_duplex */
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SHIFT                                        6
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WIDTH                                        1
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MASK                               0x00000040U
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__RESET                                        0
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field pause */
#define EMAC_REGS__PCS_AN_ADV__PAUSE__SHIFT                                              7
#define EMAC_REGS__PCS_AN_ADV__PAUSE__WIDTH                                              2
#define EMAC_REGS__PCS_AN_ADV__PAUSE__MASK                                     0x00000180U
#define EMAC_REGS__PCS_AN_ADV__PAUSE__RESET                                              0
#define EMAC_REGS__PCS_AN_ADV__PAUSE__READ(src)     (((uint32_t)(src) & 0x00000180U) >> 7)
#define EMAC_REGS__PCS_AN_ADV__PAUSE__WRITE(src)    (((uint32_t)(src) << 7) & 0x00000180U)
#define EMAC_REGS__PCS_AN_ADV__PAUSE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000180U) | (((uint32_t)(src) <<\
                    7) & 0x00000180U)
#define EMAC_REGS__PCS_AN_ADV__PAUSE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000180U)))

/* macros for field reserved_11_9 */
#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__SHIFT                                      9
#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__WIDTH                                      3
#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__MASK                             0x00000e00U
#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__RESET                                      0
#define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000e00U) >> 9)

/* macros for field remote_fault */
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__SHIFT                                      12
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WIDTH                                       2
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MASK                              0x00003000U
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__RESET                                       0
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00003000U) >> 12)
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00003000U)
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((uint32_t)(src) <<\
                    12) & 0x00003000U)
#define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field reserved_14 */
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SHIFT                                       14
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__WIDTH                                        1
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__MASK                               0x00004000U
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__RESET                                        0
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_AN_ADV__RESERVED_14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field next_page */
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SHIFT                                         15
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WIDTH                                          1
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MASK                                 0x00008000U
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__RESET                                          0
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__SHIFT                                    16
#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__WIDTH                                    16
#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__MASK                            0xffff0000U
#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__RESET                                     0
#define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_AN_ADV__TYPE                                               uint32_t
#define EMAC_REGS__PCS_AN_ADV__READ                                            0xffffffffU
#define EMAC_REGS__PCS_AN_ADV__WRITE                                           0xffffffffU

#endif /* __PCS_AN_ADV_MACRO__ */


/* macros for pcs_an_adv */
#define EMAC_REGS__INST_PCS_AN_ADV__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::pcs_an_lp_base */
#ifndef __EMAC_REGS__PCS_AN_LP_BASE_MACRO__
#define __EMAC_REGS__PCS_AN_LP_BASE_MACRO__

/* macros for field reserved_4_0 */
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__SHIFT                                   0
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__WIDTH                                   5
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__MASK                          0x0000001fU
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__RESET                                   0
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__READ(src) ((uint32_t)(src) & 0x0000001fU)

/* macros for field link_partner_full_duplex */
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SHIFT                       5
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__WIDTH                       1
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__MASK              0x00000020U
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__RESET                       0
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field link_partner_half_duplex */
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SHIFT                       6
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__WIDTH                       1
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__MASK              0x00000040U
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__RESET                       0
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field pause */
#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__SHIFT                                          7
#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__WIDTH                                          2
#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__MASK                                 0x00000180U
#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__RESET                                          0
#define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__READ(src) (((uint32_t)(src) & 0x00000180U) >> 7)

/* macros for field speed_reserved */
#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__SHIFT                                 9
#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__WIDTH                                 3
#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__MASK                        0x00000e00U
#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__RESET                                 0
#define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000e00U) >> 9)

/* macros for field link_partner_remote_fault_duplex_mode */
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__SHIFT         12
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__WIDTH          2
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__MASK 0x00003000U
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__RESET          0
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00003000U) >> 12)

/* macros for field link_partner_acknowledge */
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SHIFT                      14
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__WIDTH                       1
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__MASK              0x00004000U
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__RESET                       0
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field link_partner_next_page_status */
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SHIFT                 15
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__WIDTH                  1
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__MASK         0x00008000U
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__RESET                  0
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__SHIFT                                16
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__WIDTH                                16
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__MASK                        0xffff0000U
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__RESET                                 0
#define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_AN_LP_BASE__TYPE                                           uint32_t
#define EMAC_REGS__PCS_AN_LP_BASE__READ                                        0xffffffffU

#endif /* __PCS_AN_LP_BASE_MACRO__ */


/* macros for pcs_an_lp_base */
#define EMAC_REGS__INST_PCS_AN_LP_BASE__NUM                                              1

/* macros for BlueprintGlobalNameSpace::pcs_an_exp */
#ifndef __EMAC_REGS__PCS_AN_EXP_MACRO__
#define __EMAC_REGS__PCS_AN_EXP_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SHIFT                                         0
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__WIDTH                                         1
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__MASK                                0x00000001U
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__RESET                                         0
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__READ(src)       ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__PCS_AN_EXP__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field page_received */
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SHIFT                                      1
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__WIDTH                                      1
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__MASK                             0x00000002U
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__RESET                                      0
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field next_page_capability */
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SHIFT                               2
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__WIDTH                               1
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__MASK                      0x00000004U
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__RESET                               1
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field reserved_31_3 */
#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__SHIFT                                      3
#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__WIDTH                                     29
#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__MASK                             0xfffffff8U
#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__RESET                                      0
#define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffff8U) >> 3)
#define EMAC_REGS__PCS_AN_EXP__TYPE                                               uint32_t
#define EMAC_REGS__PCS_AN_EXP__READ                                            0xffffffffU

#endif /* __PCS_AN_EXP_MACRO__ */


/* macros for pcs_an_exp */
#define EMAC_REGS__INST_PCS_AN_EXP__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::pcs_an_np_tx */
#ifndef __EMAC_REGS__PCS_AN_NP_TX_MACRO__
#define __EMAC_REGS__PCS_AN_NP_TX_MACRO__

/* macros for field message */
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__SHIFT                                          0
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WIDTH                                         11
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MASK                                 0x000007ffU
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__RESET                                          0
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__READ(src)        ((uint32_t)(src) & 0x000007ffU)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WRITE(src)       ((uint32_t)(src) & 0x000007ffU)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((uint32_t)(src) &\
                    0x000007ffU)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field reserved_11 */
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SHIFT                                     11
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__WIDTH                                      1
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__MASK                             0x00000800U
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__RESET                                      0
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field acknowledge_2 */
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SHIFT                                   12
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WIDTH                                    1
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MASK                           0x00001000U
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__RESET                                    0
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field message_page_indicator */
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SHIFT                          13
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WIDTH                           1
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MASK                  0x00002000U
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__RESET                           0
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field reserved_14 */
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SHIFT                                     14
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__WIDTH                                      1
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__MASK                             0x00004000U
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__RESET                                      0
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field next_page_to_transmit */
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SHIFT                           15
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WIDTH                            1
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MASK                   0x00008000U
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__RESET                            0
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__SHIFT                                  16
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__WIDTH                                  16
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__MASK                          0xffff0000U
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__RESET                                   0
#define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_AN_NP_TX__TYPE                                             uint32_t
#define EMAC_REGS__PCS_AN_NP_TX__READ                                          0xffffffffU
#define EMAC_REGS__PCS_AN_NP_TX__WRITE                                         0xffffffffU

#endif /* __PCS_AN_NP_TX_MACRO__ */


/* macros for pcs_an_np_tx */
#define EMAC_REGS__INST_PCS_AN_NP_TX__NUM                                                1

/* macros for BlueprintGlobalNameSpace::pcs_an_lp_np */
#ifndef __EMAC_REGS__PCS_AN_LP_NP_MACRO__
#define __EMAC_REGS__PCS_AN_LP_NP_MACRO__

/* macros for field message */
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__SHIFT                                          0
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__WIDTH                                         11
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__MASK                                 0x000007ffU
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__RESET                                          0
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__READ(src)        ((uint32_t)(src) & 0x000007ffU)

/* macros for field toggle */
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SHIFT                                          11
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__WIDTH                                           1
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__MASK                                  0x00000800U
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__RESET                                           0
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__READ(src) (((uint32_t)(src) & 0x00000800U) >> 11)
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field acknowledge_2 */
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SHIFT                                   12
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__WIDTH                                    1
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__MASK                           0x00001000U
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__RESET                                    0
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field message_page_indicator */
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SHIFT                          13
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__WIDTH                           1
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__MASK                  0x00002000U
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__RESET                           0
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field acknowledge */
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SHIFT                                     14
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__WIDTH                                      1
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__MASK                             0x00004000U
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__RESET                                      0
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field next_page_to_receive */
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SHIFT                            15
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__WIDTH                             1
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__MASK                    0x00008000U
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__RESET                             0
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__SHIFT                                  16
#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__WIDTH                                  16
#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__MASK                          0xffff0000U
#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__RESET                                   0
#define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_AN_LP_NP__TYPE                                             uint32_t
#define EMAC_REGS__PCS_AN_LP_NP__READ                                          0xffffffffU

#endif /* __PCS_AN_LP_NP_MACRO__ */


/* macros for pcs_an_lp_np */
#define EMAC_REGS__INST_PCS_AN_LP_NP__NUM                                                1

/* macros for BlueprintGlobalNameSpace::pcs_an_ext_status */
#ifndef __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__
#define __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__

/* macros for field reserved_11_0 */
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__SHIFT                               0
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__WIDTH                              12
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__MASK                      0x00000fffU
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__RESET                               0
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000fffU)

/* macros for field half_duplex_1000base_t */
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SHIFT                     12
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__WIDTH                      1
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__MASK             0x00001000U
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__RESET                      0
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field full_duplex_1000base_t */
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SHIFT                     13
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__WIDTH                      1
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__MASK             0x00002000U
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__RESET                      0
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field half_duplex_1000base_x */
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SHIFT                     14
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__WIDTH                      1
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__MASK             0x00004000U
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__RESET                      0
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field full_duplex_1000base_x */
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SHIFT                     15
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__WIDTH                      1
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__MASK             0x00008000U
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__RESET                      1
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__SHIFT                             16
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__WIDTH                             16
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__MASK                     0xffff0000U
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__RESET                              0
#define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__PCS_AN_EXT_STATUS__TYPE                                        uint32_t
#define EMAC_REGS__PCS_AN_EXT_STATUS__READ                                     0xffffffffU

#endif /* __PCS_AN_EXT_STATUS_MACRO__ */


/* macros for pcs_an_ext_status */
#define EMAC_REGS__INST_PCS_AN_EXT_STATUS__NUM                                           1

/* macros for BlueprintGlobalNameSpace::tx_pause_quantum1 */
#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__
#define __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__

/* macros for field quantum_p2 */
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__SHIFT                                  0
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MASK                         0x0000ffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field quantum_p3 */
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__SHIFT                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MASK                         0xffff0000U
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__TX_PAUSE_QUANTUM1__TYPE                                        uint32_t
#define EMAC_REGS__TX_PAUSE_QUANTUM1__READ                                     0xffffffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM1__WRITE                                    0xffffffffU

#endif /* __TX_PAUSE_QUANTUM1_MACRO__ */


/* macros for tx_pause_quantum1 */
#define EMAC_REGS__INST_TX_PAUSE_QUANTUM1__NUM                                           1

/* macros for BlueprintGlobalNameSpace::tx_pause_quantum2 */
#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__
#define __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__

/* macros for field quantum_p4 */
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__SHIFT                                  0
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MASK                         0x0000ffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field quantum_p5 */
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__SHIFT                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MASK                         0xffff0000U
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__TX_PAUSE_QUANTUM2__TYPE                                        uint32_t
#define EMAC_REGS__TX_PAUSE_QUANTUM2__READ                                     0xffffffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM2__WRITE                                    0xffffffffU

#endif /* __TX_PAUSE_QUANTUM2_MACRO__ */


/* macros for tx_pause_quantum2 */
#define EMAC_REGS__INST_TX_PAUSE_QUANTUM2__NUM                                           1

/* macros for BlueprintGlobalNameSpace::tx_pause_quantum3 */
#ifndef __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__
#define __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__

/* macros for field quantum_p6 */
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__SHIFT                                  0
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MASK                         0x0000ffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field quantum_p7 */
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__SHIFT                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WIDTH                                 16
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MASK                         0xffff0000U
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__RESET                             0xFFFF
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__TX_PAUSE_QUANTUM3__TYPE                                        uint32_t
#define EMAC_REGS__TX_PAUSE_QUANTUM3__READ                                     0xffffffffU
#define EMAC_REGS__TX_PAUSE_QUANTUM3__WRITE                                    0xffffffffU

#endif /* __TX_PAUSE_QUANTUM3_MACRO__ */


/* macros for tx_pause_quantum3 */
#define EMAC_REGS__INST_TX_PAUSE_QUANTUM3__NUM                                           1

/* macros for BlueprintGlobalNameSpace::pfc_status */
#ifndef __EMAC_REGS__PFC_STATUS_MACRO__
#define __EMAC_REGS__PFC_STATUS_MACRO__

/* macros for field rx_pfc_paused */
#define EMAC_REGS__PFC_STATUS__RX_PFC_PAUSED__SHIFT                                      0
#define EMAC_REGS__PFC_STATUS__RX_PFC_PAUSED__WIDTH                                      8
#define EMAC_REGS__PFC_STATUS__RX_PFC_PAUSED__MASK                             0x000000ffU
#define EMAC_REGS__PFC_STATUS__RX_PFC_PAUSED__RESET                                      0
#define EMAC_REGS__PFC_STATUS__RX_PFC_PAUSED__READ(src)    ((uint32_t)(src) & 0x000000ffU)

/* macros for field pfc_negotiate_pclk */
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__SHIFT                                 8
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__WIDTH                                 1
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__MASK                        0x00000100U
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__RESET                                 0
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__PFC_STATUS__PFC_NEGOTIATE_PCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_31_9 */
#define EMAC_REGS__PFC_STATUS__RESERVED_31_9__SHIFT                                      9
#define EMAC_REGS__PFC_STATUS__RESERVED_31_9__WIDTH                                     23
#define EMAC_REGS__PFC_STATUS__RESERVED_31_9__MASK                             0xfffffe00U
#define EMAC_REGS__PFC_STATUS__RESERVED_31_9__RESET                                      0
#define EMAC_REGS__PFC_STATUS__RESERVED_31_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffe00U) >> 9)
#define EMAC_REGS__PFC_STATUS__TYPE                                               uint32_t
#define EMAC_REGS__PFC_STATUS__READ                                            0xffffffffU

#endif /* __PFC_STATUS_MACRO__ */


/* macros for pfc_status */
#define EMAC_REGS__INST_PFC_STATUS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::rx_lpi */
#ifndef __EMAC_REGS__RX_LPI_MACRO__
#define __EMAC_REGS__RX_LPI_MACRO__

/* macros for field count */
#define EMAC_REGS__RX_LPI__COUNT__SHIFT                                                  0
#define EMAC_REGS__RX_LPI__COUNT__WIDTH                                                 16
#define EMAC_REGS__RX_LPI__COUNT__MASK                                         0x0000ffffU
#define EMAC_REGS__RX_LPI__COUNT__RESET                                                  0
#define EMAC_REGS__RX_LPI__COUNT__READ(src)                ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__RX_LPI__RESERVED_31_16__SHIFT                                        16
#define EMAC_REGS__RX_LPI__RESERVED_31_16__WIDTH                                        16
#define EMAC_REGS__RX_LPI__RESERVED_31_16__MASK                                0xffff0000U
#define EMAC_REGS__RX_LPI__RESERVED_31_16__RESET                                         0
#define EMAC_REGS__RX_LPI__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__RX_LPI__TYPE                                                   uint32_t
#define EMAC_REGS__RX_LPI__READ                                                0xffffffffU
#define EMAC_REGS__RX_LPI__RCLR                                                0x0000ffffU

#endif /* __RX_LPI_MACRO__ */


/* macros for rx_lpi */
#define EMAC_REGS__INST_RX_LPI__NUM                                                      1

/* macros for BlueprintGlobalNameSpace::rx_lpi_time */
#ifndef __EMAC_REGS__RX_LPI_TIME_MACRO__
#define __EMAC_REGS__RX_LPI_TIME_MACRO__

/* macros for field lpi_time */
#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__SHIFT                                          0
#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__WIDTH                                         24
#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__MASK                                 0x00ffffffU
#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__RESET                                          0
#define EMAC_REGS__RX_LPI_TIME__LPI_TIME__READ(src)        ((uint32_t)(src) & 0x00ffffffU)

/* macros for field reserved_31_24 */
#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__SHIFT                                   24
#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__WIDTH                                    8
#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__MASK                           0xff000000U
#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__RESET                                    0
#define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__RX_LPI_TIME__TYPE                                              uint32_t
#define EMAC_REGS__RX_LPI_TIME__READ                                           0xffffffffU
#define EMAC_REGS__RX_LPI_TIME__RCLR                                           0x00ffffffU

#endif /* __RX_LPI_TIME_MACRO__ */


/* macros for rx_lpi_time */
#define EMAC_REGS__INST_RX_LPI_TIME__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::tx_lpi */
#ifndef __EMAC_REGS__TX_LPI_MACRO__
#define __EMAC_REGS__TX_LPI_MACRO__

/* macros for field count */
#define EMAC_REGS__TX_LPI__COUNT__SHIFT                                                  0
#define EMAC_REGS__TX_LPI__COUNT__WIDTH                                                 16
#define EMAC_REGS__TX_LPI__COUNT__MASK                                         0x0000ffffU
#define EMAC_REGS__TX_LPI__COUNT__RESET                                                  0
#define EMAC_REGS__TX_LPI__COUNT__READ(src)                ((uint32_t)(src) & 0x0000ffffU)

/* macros for field reserved_31_16 */
#define EMAC_REGS__TX_LPI__RESERVED_31_16__SHIFT                                        16
#define EMAC_REGS__TX_LPI__RESERVED_31_16__WIDTH                                        16
#define EMAC_REGS__TX_LPI__RESERVED_31_16__MASK                                0xffff0000U
#define EMAC_REGS__TX_LPI__RESERVED_31_16__RESET                                         0
#define EMAC_REGS__TX_LPI__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TX_LPI__TYPE                                                   uint32_t
#define EMAC_REGS__TX_LPI__READ                                                0xffffffffU
#define EMAC_REGS__TX_LPI__RCLR                                                0x0000ffffU

#endif /* __TX_LPI_MACRO__ */


/* macros for tx_lpi */
#define EMAC_REGS__INST_TX_LPI__NUM                                                      1

/* macros for BlueprintGlobalNameSpace::tx_lpi_time */
#ifndef __EMAC_REGS__TX_LPI_TIME_MACRO__
#define __EMAC_REGS__TX_LPI_TIME_MACRO__

/* macros for field lpi_time */
#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__SHIFT                                          0
#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__WIDTH                                         24
#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__MASK                                 0x00ffffffU
#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__RESET                                          0
#define EMAC_REGS__TX_LPI_TIME__LPI_TIME__READ(src)        ((uint32_t)(src) & 0x00ffffffU)

/* macros for field reserved_31_24 */
#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__SHIFT                                   24
#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__WIDTH                                    8
#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__MASK                           0xff000000U
#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__RESET                                    0
#define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__TX_LPI_TIME__TYPE                                              uint32_t
#define EMAC_REGS__TX_LPI_TIME__READ                                           0xffffffffU
#define EMAC_REGS__TX_LPI_TIME__RCLR                                           0x00ffffffU

#endif /* __TX_LPI_TIME_MACRO__ */


/* macros for tx_lpi_time */
#define EMAC_REGS__INST_TX_LPI_TIME__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::designcfg_debug1 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__

/* macros for field no_pcs */
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SHIFT                                       0
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__WIDTH                                       1
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__MASK                              0x00000001U
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__RESET                                       0
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__READ(src)     ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field exclude_qbv */
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SHIFT                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__WIDTH                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__MASK                         0x00000002U
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__RESET                                  0
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_3_2 */
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__SHIFT                                 2
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__WIDTH                                 2
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__MASK                        0x0000000cU
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__RESET                                 0
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000000cU) >> 2)

/* macros for field int_loopback */
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SHIFT                                 4
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__WIDTH                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__MASK                        0x00000010U
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__RESET                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field reserved_5 */
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SHIFT                                   5
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__WIDTH                                   1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__MASK                          0x00000020U
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__RESET                                   0
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field ext_fifo_interface */
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SHIFT                           6
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__WIDTH                           1
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__MASK                  0x00000040U
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__RESET                           0
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_7 */
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SHIFT                                   7
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__WIDTH                                   1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__MASK                          0x00000080U
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__RESET                                   0
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_8 */
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SHIFT                                   8
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__WIDTH                                   1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__MASK                          0x00000100U
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__RESET                                   1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field user_io */
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SHIFT                                      9
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__WIDTH                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__MASK                             0x00000200U
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__RESET                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field user_out_width */
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__SHIFT                              10
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__WIDTH                               5
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__MASK                      0x00007c00U
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__RESET                              16
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00007c00U) >> 10)

/* macros for field user_in_width */
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__SHIFT                               15
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__WIDTH                                5
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__MASK                       0x000f8000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__RESET                               16
#define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f8000U) >> 15)

/* macros for field reserved_20 */
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SHIFT                                 20
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__WIDTH                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__MASK                         0x00100000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__RESET                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field no_stats */
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SHIFT                                    21
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__WIDTH                                     1
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__MASK                            0x00200000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__RESET                                     0
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field no_snapshot */
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SHIFT                                 22
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__WIDTH                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__MASK                         0x00400000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__RESET                                  0
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field irq_read_clear */
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SHIFT                              23
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__WIDTH                               1
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__MASK                      0x00800000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__RESET                               1
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field exclude_cbs */
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SHIFT                                 24
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__WIDTH                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__MASK                         0x01000000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__RESET                                  0
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field dma_bus_width */
#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__SHIFT                               25
#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__WIDTH                                3
#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__MASK                       0x0e000000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__RESET                                2
#define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0e000000U) >> 25)

/* macros for field axi_cache_value */
#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__SHIFT                             28
#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__WIDTH                              4
#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__MASK                     0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__RESET                              0
#define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG1__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG1__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG1_MACRO__ */


/* macros for designcfg_debug1 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG1__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug2 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__

/* macros for field jumbo_max_length */
#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__SHIFT                             0
#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__WIDTH                            14
#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__MASK                    0x00003fffU
#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__RESET                         10240
#define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)

/* macros for field reserved_15_14 */
#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__SHIFT                              14
#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__WIDTH                               2
#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__MASK                      0x0000c000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000c000U) >> 14)

/* macros for field hprot_value */
#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__SHIFT                                 16
#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__WIDTH                                  4
#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__MASK                         0x000f0000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__RESET                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field rx_pkt_buffer */
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SHIFT                               20
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__WIDTH                                1
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__MASK                       0x00100000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__RESET                                1
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field tx_pkt_buffer */
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SHIFT                               21
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__WIDTH                                1
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__MASK                       0x00200000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__RESET                                1
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field rx_pbuf_addr */
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__SHIFT                                22
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__WIDTH                                 4
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__MASK                        0x03c00000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__RESET                                11
#define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x03c00000U) >> 22)

/* macros for field tx_pbuf_addr */
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__SHIFT                                26
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__WIDTH                                 4
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__MASK                        0x3c000000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__RESET                                14
#define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3c000000U) >> 26)

/* macros for field axi */
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SHIFT                                         30
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__WIDTH                                          1
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__MASK                                 0x40000000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__RESET                                          1
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field spram */
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SHIFT                                       31
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__WIDTH                                        1
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__MASK                               0x80000000U
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__RESET                                        0
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__DESIGNCFG_DEBUG2__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG2__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG2_MACRO__ */


/* macros for designcfg_debug2 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG2__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug3 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__

/* macros for field reserved_20_0 */
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_20_0__SHIFT                                0
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_20_0__WIDTH                               21
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_20_0__MASK                       0x001fffffU
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_20_0__RESET                                0
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_20_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x001fffffU)

/* macros for field reserved_23_21 */
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_21__SHIFT                              21
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_21__WIDTH                               3
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_21__MASK                      0x00e00000U
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_21__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_21__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00e00000U) >> 21)

/* macros for field num_spec_add_filters */
#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__SHIFT                        24
#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__WIDTH                         6
#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__MASK                0x3f000000U
#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__RESET                        36
#define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3f000000U) >> 24)

/* macros for field reserved_31_30 */
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__SHIFT                              30
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__WIDTH                               2
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__MASK                      0xc0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__DESIGNCFG_DEBUG3__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG3__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG3_MACRO__ */


/* macros for designcfg_debug3 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG3__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug4 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__

/* macros for field reserved_19_0 */
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_19_0__SHIFT                                0
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_19_0__WIDTH                               20
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_19_0__MASK                       0x000fffffU
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_19_0__RESET                                0
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_19_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000fffffU)

/* macros for field reserved_31_20 */
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_20__SHIFT                              20
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_20__WIDTH                              12
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_20__MASK                      0xfff00000U
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_20__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_20__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfff00000U) >> 20)
#define EMAC_REGS__DESIGNCFG_DEBUG4__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG4__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG4_MACRO__ */


/* macros for designcfg_debug4 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG4__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug5 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__

/* macros for field rx_fifo_cnt_width */
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__SHIFT                            0
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__WIDTH                            4
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__MASK                   0x0000000fU
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__RESET                            5
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)

/* macros for field tx_fifo_cnt_width */
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__SHIFT                            4
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__WIDTH                            4
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__MASK                   0x000000f0U
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__RESET                            4
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field tsu */
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SHIFT                                          8
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__WIDTH                                          1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__MASK                                 0x00000100U
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__RESET                                          1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__READ(src) (((uint32_t)(src) & 0x00000100U) >> 8)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field phy_ident */
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SHIFT                                    9
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__WIDTH                                    1
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__MASK                           0x00000200U
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__RESET                                    1
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field dma_bus_width_def */
#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__SHIFT                           10
#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__WIDTH                            2
#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__MASK                   0x00000c00U
#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__RESET                            0
#define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000c00U) >> 10)

/* macros for field mdc_clock_div */
#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__SHIFT                               12
#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__WIDTH                                3
#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__MASK                       0x00007000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__RESET                                2
#define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00007000U) >> 12)

/* macros for field endian_swap_def */
#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__SHIFT                             15
#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__WIDTH                              2
#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__MASK                     0x00018000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__RESET                              0
#define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00018000U) >> 15)

/* macros for field rx_pbuf_size_def */
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__SHIFT                            17
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__WIDTH                             2
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__MASK                    0x00060000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__RESET                             3
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00060000U) >> 17)

/* macros for field tx_pbuf_size_def */
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SHIFT                            19
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__WIDTH                             1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__MASK                    0x00080000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__RESET                             1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field rx_buffer_length_def */
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__SHIFT                        20
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__WIDTH                         8
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__MASK                0x0ff00000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__RESET                         2
#define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0ff00000U) >> 20)

/* macros for field tsu_clk */
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SHIFT                                     28
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__WIDTH                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__MASK                             0x10000000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__RESET                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field axi_prot_value */
#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__SHIFT                              29
#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__WIDTH                               3
#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__MASK                      0xe0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__RESET                               2
#define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0xe0000000U) >> 29)
#define EMAC_REGS__DESIGNCFG_DEBUG5__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG5__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG5_MACRO__ */


/* macros for designcfg_debug5 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG5__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug6 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SHIFT                                   0
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__WIDTH                                   1
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__MASK                          0x00000001U
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__RESET                                   0
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__READ(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field dma_priority_queue1 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SHIFT                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__MASK                 0x00000002U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_priority_queue2 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SHIFT                          2
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__MASK                 0x00000004U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field dma_priority_queue3 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SHIFT                          3
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__MASK                 0x00000008U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field dma_priority_queue4 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SHIFT                          4
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__MASK                 0x00000010U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field dma_priority_queue5 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SHIFT                          5
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__MASK                 0x00000020U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field dma_priority_queue6 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SHIFT                          6
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__MASK                 0x00000040U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field dma_priority_queue7 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SHIFT                          7
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__MASK                 0x00000080U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field dma_priority_queue8 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SHIFT                          8
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__MASK                 0x00000100U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field dma_priority_queue9 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SHIFT                          9
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__MASK                 0x00000200U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field dma_priority_queue10 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SHIFT                        10
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__MASK                0x00000400U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field dma_priority_queue11 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SHIFT                        11
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__MASK                0x00000800U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field dma_priority_queue12 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SHIFT                        12
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__MASK                0x00001000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field dma_priority_queue13 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SHIFT                        13
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__MASK                0x00002000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field dma_priority_queue14 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SHIFT                        14
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__MASK                0x00004000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field dma_priority_queue15 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SHIFT                        15
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__MASK                0x00008000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__RESET                         1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field tx_pbuf_queue_segment_size */
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__SHIFT                  16
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__WIDTH                   4
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__MASK          0x000f0000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__RESET                   4
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field ext_tsu_timer */
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SHIFT                               20
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__WIDTH                                1
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__MASK                       0x00100000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__RESET                                1
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field tx_add_fifo_if */
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SHIFT                              21
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__WIDTH                               1
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__MASK                      0x00200000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field host_if_soft_select */
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SHIFT                         22
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__MASK                 0x00400000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field dma_addr_width_is_64b */
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SHIFT                       23
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__WIDTH                        1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__MASK               0x00800000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__RESET                        1
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field pfc_multi_quantum */
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SHIFT                           24
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__WIDTH                            1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__MASK                   0x01000000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__RESET                            1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field pbuf_cutthru */
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SHIFT                                25
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__WIDTH                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__MASK                        0x02000000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__RESET                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field pbuf_rsc */
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SHIFT                                    26
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__WIDTH                                     1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__MASK                            0x04000000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__RESET                                     1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field pbuf_lso */
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SHIFT                                    27
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__WIDTH                                     1
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__MASK                            0x08000000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__RESET                                     0
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field reserved_31_28 */
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__SHIFT                              28
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__WIDTH                               4
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__MASK                      0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG6__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG6__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG6_MACRO__ */


/* macros for designcfg_debug6 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG6__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug7 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__

/* macros for field tx_pbuf_num_segments_q0 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__SHIFT                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__MASK             0x0000000fU
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)

/* macros for field tx_pbuf_num_segments_q1 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__SHIFT                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__MASK             0x000000f0U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field tx_pbuf_num_segments_q2 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__SHIFT                      8
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__MASK             0x00000f00U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)

/* macros for field tx_pbuf_num_segments_q3 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__SHIFT                     12
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__MASK             0x0000f000U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)

/* macros for field tx_pbuf_num_segments_q4 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__SHIFT                     16
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__MASK             0x000f0000U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field tx_pbuf_num_segments_q5 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__SHIFT                     20
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__MASK             0x00f00000U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)

/* macros for field tx_pbuf_num_segments_q6 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__SHIFT                     24
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__MASK             0x0f000000U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)

/* macros for field tx_pbuf_num_segments_q7 */
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__SHIFT                     28
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__MASK             0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG7__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG7__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG7_MACRO__ */


/* macros for designcfg_debug7 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG7__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug8 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__

/* macros for field num_scr2_compare_regs */
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__SHIFT                        0
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__WIDTH                        8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__MASK               0x000000ffU
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__RESET                       32
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field num_scr2_ethtype_regs */
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__SHIFT                        8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__WIDTH                        8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__MASK               0x0000ff00U
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__RESET                        8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field num_type2_screeners */
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__SHIFT                         16
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__WIDTH                          8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__MASK                 0x00ff0000U
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__RESET                         16
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field num_type1_screeners */
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__SHIFT                         24
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__WIDTH                          8
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__MASK                 0xff000000U
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__RESET                         16
#define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__DESIGNCFG_DEBUG8__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG8__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG8_MACRO__ */


/* macros for designcfg_debug8 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG8__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug9 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__

/* macros for field tx_pbuf_num_segments_q8 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__SHIFT                      0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__MASK             0x0000000fU
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)

/* macros for field tx_pbuf_num_segments_q9 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__SHIFT                      4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__WIDTH                      4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__MASK             0x000000f0U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__RESET                      0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field tx_pbuf_num_segments_q10 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__SHIFT                     8
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__MASK            0x00000f00U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)

/* macros for field tx_pbuf_num_segments_q11 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__SHIFT                    12
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__MASK            0x0000f000U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)

/* macros for field tx_pbuf_num_segments_q12 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__SHIFT                    16
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__MASK            0x000f0000U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field tx_pbuf_num_segments_q13 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__SHIFT                    20
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__MASK            0x00f00000U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)

/* macros for field tx_pbuf_num_segments_q14 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__SHIFT                    24
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__MASK            0x0f000000U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)

/* macros for field tx_pbuf_num_segments_q15 */
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__SHIFT                    28
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__WIDTH                     4
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__MASK            0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__RESET                     0
#define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG9__TYPE                                         uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG9__READ                                      0xffffffffU

#endif /* __DESIGNCFG_DEBUG9_MACRO__ */


/* macros for designcfg_debug9 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG9__NUM                                            1

/* macros for BlueprintGlobalNameSpace::designcfg_debug10 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__

/* macros for field axi_rx_descr_wr_buff_bits */
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__SHIFT                   0
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__WIDTH                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__MASK          0x0000000fU
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__RESET                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)

/* macros for field axi_tx_descr_wr_buff_bits */
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__SHIFT                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__WIDTH                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__MASK          0x000000f0U
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__RESET                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field axi_rx_descr_rd_buff_bits */
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__SHIFT                   8
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__WIDTH                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__MASK          0x00000f00U
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__RESET                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)

/* macros for field axi_tx_descr_rd_buff_bits */
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__SHIFT                  12
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__WIDTH                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__MASK          0x0000f000U
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__RESET                   4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)

/* macros for field axi_access_pipeline_bits */
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__SHIFT                   16
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__WIDTH                    4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__MASK           0x000f0000U
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__RESET                    4
#define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field rx_pbuf_data */
#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__SHIFT                               20
#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__WIDTH                                4
#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__MASK                       0x00f00000U
#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__RESET                                2
#define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)

/* macros for field tx_pbuf_data */
#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__SHIFT                               24
#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__WIDTH                                4
#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__MASK                       0x0f000000U
#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__RESET                                2
#define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)

/* macros for field emac_bus_width */
#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__SHIFT                             28
#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__WIDTH                              4
#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__MASK                     0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__RESET                              4
#define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG10__TYPE                                        uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG10__READ                                     0xffffffffU

#endif /* __DESIGNCFG_DEBUG10_MACRO__ */


/* macros for designcfg_debug10 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG10__NUM                                           1

/* macros for BlueprintGlobalNameSpace::designcfg_debug11 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG11_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG11_MACRO__

/* macros for field ecc_sram */
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__SHIFT                                    0
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__WIDTH                                    1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__MASK                           0x00000001U
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__RESET                                    1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__READ(src)  ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ECC_SRAM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field dap_protection */
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__SHIFT                              1
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__WIDTH                              1
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__MASK                     0x00000002U
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__RESET                              1
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__DESIGNCFG_DEBUG11__DAP_PROTECTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field csr_protection */
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__SHIFT                              2
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__WIDTH                              1
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__MASK                     0x00000004U
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__RESET                              1
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__DESIGNCFG_DEBUG11__CSR_PROTECTION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field protect_tsu */
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__SHIFT                                 3
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__WIDTH                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__MASK                        0x00000008U
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__RESET                                 1
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__DESIGNCFG_DEBUG11__PROTECT_TSU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field asf_integrity_prot */
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__SHIFT                          4
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__MASK                 0x00000010U
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__RESET                          1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_INTEGRITY_PROT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field asf_trans_to_prot */
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__SHIFT                           5
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__WIDTH                           1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__MASK                  0x00000020U
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__RESET                           1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_TRANS_TO_PROT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field asf_host_par */
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__SHIFT                                6
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__WIDTH                                1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__MASK                       0x00000040U
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__RESET                                1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_HOST_PAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field asf_prot_tx_sched */
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__SHIFT                           7
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__WIDTH                           1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__MASK                  0x00000080U
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__RESET                           1
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__DESIGNCFG_DEBUG11__ASF_PROT_TX_SCHED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_31_8 */
#define EMAC_REGS__DESIGNCFG_DEBUG11__RESERVED_31_8__SHIFT                               8
#define EMAC_REGS__DESIGNCFG_DEBUG11__RESERVED_31_8__WIDTH                              24
#define EMAC_REGS__DESIGNCFG_DEBUG11__RESERVED_31_8__MASK                      0xffffff00U
#define EMAC_REGS__DESIGNCFG_DEBUG11__RESERVED_31_8__RESET                               0
#define EMAC_REGS__DESIGNCFG_DEBUG11__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__DESIGNCFG_DEBUG11__TYPE                                        uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG11__READ                                     0xffffffffU

#endif /* __DESIGNCFG_DEBUG11_MACRO__ */


/* macros for designcfg_debug11 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG11__NUM                                           1

/* macros for BlueprintGlobalNameSpace::designcfg_debug12 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG12_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG12_MACRO__

/* macros for field gem_num_cb_streams */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__SHIFT                          0
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__WIDTH                          8
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__MASK                 0x000000ffU
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__RESET                         16
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field gem_cb_history_len */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__SHIFT                          8
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__WIDTH                          8
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__MASK                 0x0000ff00U
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__RESET                         64
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field gem_has_cb */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__SHIFT                                 16
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__WIDTH                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__MASK                         0x00010000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__RESET                                  1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_CB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field emac_rx_pbuf_addr */
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__SHIFT                          17
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__WIDTH                           4
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__MASK                  0x001e0000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__RESET                          11
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x001e0000U) >> 17)

/* macros for field emac_tx_pbuf_addr */
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__SHIFT                          21
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__WIDTH                           4
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__MASK                  0x01e00000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__RESET                          11
#define EMAC_REGS__DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01e00000U) >> 21)

/* macros for field gem_has_802p3_br */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__SHIFT                           25
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__WIDTH                            1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__MASK                   0x02000000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__RESET                            1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field gem_high_speed */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__SHIFT                             26
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__WIDTH                              1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__MASK                     0x04000000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__RESET                              1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field gem_vm */
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__SHIFT                                     27
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__WIDTH                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__MASK                             0x08000000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__RESET                                      1
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__DESIGNCFG_DEBUG12__GEM_VM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field reserved_31_28 */
#define EMAC_REGS__DESIGNCFG_DEBUG12__RESERVED_31_28__SHIFT                             28
#define EMAC_REGS__DESIGNCFG_DEBUG12__RESERVED_31_28__WIDTH                              4
#define EMAC_REGS__DESIGNCFG_DEBUG12__RESERVED_31_28__MASK                     0xf0000000U
#define EMAC_REGS__DESIGNCFG_DEBUG12__RESERVED_31_28__RESET                              0
#define EMAC_REGS__DESIGNCFG_DEBUG12__RESERVED_31_28__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__DESIGNCFG_DEBUG12__TYPE                                        uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG12__READ                                     0xffffffffU

#endif /* __DESIGNCFG_DEBUG12_MACRO__ */


/* macros for designcfg_debug12 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG12__NUM                                           1

/* macros for BlueprintGlobalNameSpace::designcfg_debug13 */
#ifndef __EMAC_REGS__DESIGNCFG_DEBUG13_MACRO__
#define __EMAC_REGS__DESIGNCFG_DEBUG13_MACRO__

/* macros for field gem_pcs_srd_if */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_SRD_IF__SHIFT                              0
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_SRD_IF__WIDTH                              8
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_SRD_IF__MASK                     0x000000ffU
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_SRD_IF__RESET                             20
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_SRD_IF__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field gem_pcs_16b_on_20b */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__SHIFT                          8
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__WIDTH                          1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__MASK                 0x00000100U
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__RESET                          0
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_PCS_16B_ON_20B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field gem_usx_include_fec */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__SHIFT                         9
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__WIDTH                         1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__MASK                0x00000200U
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__RESET                         0
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_INCLUDE_FEC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field gem_usx_no_txsync */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__SHIFT                          10
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__WIDTH                           1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__MASK                  0x00000400U
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__RESET                           1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_NO_TXSYNC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field gem_usx_sync_gbx */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__SHIFT                           11
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__WIDTH                            1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__MASK                   0x00000800U
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__RESET                            0
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_USX_SYNC_GBX__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field gem_num_axi_ids */
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_NUM_AXI_IDS__SHIFT                            12
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_NUM_AXI_IDS__WIDTH                             6
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_NUM_AXI_IDS__MASK                    0x0003f000U
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_NUM_AXI_IDS__RESET                             1
#define EMAC_REGS__DESIGNCFG_DEBUG13__GEM_NUM_AXI_IDS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0003f000U) >> 12)

/* macros for field reserved_31_18 */
#define EMAC_REGS__DESIGNCFG_DEBUG13__RESERVED_31_18__SHIFT                             18
#define EMAC_REGS__DESIGNCFG_DEBUG13__RESERVED_31_18__WIDTH                             14
#define EMAC_REGS__DESIGNCFG_DEBUG13__RESERVED_31_18__MASK                     0xfffc0000U
#define EMAC_REGS__DESIGNCFG_DEBUG13__RESERVED_31_18__RESET                              0
#define EMAC_REGS__DESIGNCFG_DEBUG13__RESERVED_31_18__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffc0000U) >> 18)
#define EMAC_REGS__DESIGNCFG_DEBUG13__TYPE                                        uint32_t
#define EMAC_REGS__DESIGNCFG_DEBUG13__READ                                     0xffffffffU

#endif /* __DESIGNCFG_DEBUG13_MACRO__ */


/* macros for designcfg_debug13 */
#define EMAC_REGS__INST_DESIGNCFG_DEBUG13__NUM                                           1

/* macros for BlueprintGlobalNameSpace::axi_qos_cfg_0 */
#ifndef __EMAC_REGS__AXI_QOS_CFG_0_MACRO__
#define __EMAC_REGS__AXI_QOS_CFG_0_MACRO__

/* macros for field q_0_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__SHIFT                                    0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__MASK                           0x0000000fU
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__READ(src)  ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__WRITE(src) ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DATA_QOS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_0_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__SHIFT                                   4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__MASK                          0x000000f0U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_0_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_1_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__SHIFT                                    8
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__MASK                           0x00000f00U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_1_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__SHIFT                                  12
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__MASK                          0x0000f000U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_1_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_2_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__SHIFT                                   16
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__MASK                           0x000f0000U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_2_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__SHIFT                                  20
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__MASK                          0x00f00000U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_2_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_3_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__SHIFT                                   24
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__MASK                           0x0f000000U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_3_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__SHIFT                                  28
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__MASK                          0xf0000000U
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_0__Q_3_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__AXI_QOS_CFG_0__TYPE                                            uint32_t
#define EMAC_REGS__AXI_QOS_CFG_0__READ                                         0xffffffffU
#define EMAC_REGS__AXI_QOS_CFG_0__WRITE                                        0xffffffffU

#endif /* __AXI_QOS_CFG_0_MACRO__ */


/* macros for axi_qos_cfg_0 */
#define EMAC_REGS__INST_AXI_QOS_CFG_0__NUM                                               1

/* macros for BlueprintGlobalNameSpace::axi_qos_cfg_1 */
#ifndef __EMAC_REGS__AXI_QOS_CFG_1_MACRO__
#define __EMAC_REGS__AXI_QOS_CFG_1_MACRO__

/* macros for field q_4_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__SHIFT                                    0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__MASK                           0x0000000fU
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__READ(src)  ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__WRITE(src) ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DATA_QOS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_4_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__SHIFT                                   4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__MASK                          0x000000f0U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_4_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_5_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__SHIFT                                    8
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__MASK                           0x00000f00U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_5_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__SHIFT                                  12
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__MASK                          0x0000f000U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_5_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_6_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__SHIFT                                   16
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__MASK                           0x000f0000U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_6_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__SHIFT                                  20
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__MASK                          0x00f00000U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_6_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_7_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__SHIFT                                   24
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__MASK                           0x0f000000U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_7_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__SHIFT                                  28
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__MASK                          0xf0000000U
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_1__Q_7_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__AXI_QOS_CFG_1__TYPE                                            uint32_t
#define EMAC_REGS__AXI_QOS_CFG_1__READ                                         0xffffffffU
#define EMAC_REGS__AXI_QOS_CFG_1__WRITE                                        0xffffffffU

#endif /* __AXI_QOS_CFG_1_MACRO__ */


/* macros for axi_qos_cfg_1 */
#define EMAC_REGS__INST_AXI_QOS_CFG_1__NUM                                               1

/* macros for BlueprintGlobalNameSpace::axi_qos_cfg_2 */
#ifndef __EMAC_REGS__AXI_QOS_CFG_2_MACRO__
#define __EMAC_REGS__AXI_QOS_CFG_2_MACRO__

/* macros for field q_8_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__SHIFT                                    0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__MASK                           0x0000000fU
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__READ(src)  ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__WRITE(src) ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DATA_QOS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_8_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__SHIFT                                   4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__MASK                          0x000000f0U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_8_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_9_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__SHIFT                                    8
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__WIDTH                                    4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__MASK                           0x00000f00U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__RESET                                    0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_9_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__SHIFT                                  12
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__MASK                          0x0000f000U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_9_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_10_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__SHIFT                                  16
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__MASK                          0x000f0000U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_10_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__SHIFT                                 20
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__MASK                         0x00f00000U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_10_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_11_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__SHIFT                                  24
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__MASK                          0x0f000000U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_11_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__SHIFT                                 28
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__MASK                         0xf0000000U
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_2__Q_11_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__AXI_QOS_CFG_2__TYPE                                            uint32_t
#define EMAC_REGS__AXI_QOS_CFG_2__READ                                         0xffffffffU
#define EMAC_REGS__AXI_QOS_CFG_2__WRITE                                        0xffffffffU

#endif /* __AXI_QOS_CFG_2_MACRO__ */


/* macros for axi_qos_cfg_2 */
#define EMAC_REGS__INST_AXI_QOS_CFG_2__NUM                                               1

/* macros for BlueprintGlobalNameSpace::axi_qos_cfg_3 */
#ifndef __EMAC_REGS__AXI_QOS_CFG_3_MACRO__
#define __EMAC_REGS__AXI_QOS_CFG_3_MACRO__

/* macros for field q_12_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__SHIFT                                   0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__MASK                          0x0000000fU
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__READ(src) ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DATA_QOS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_12_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__SHIFT                                  4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__MASK                         0x000000f0U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_12_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_13_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__SHIFT                                   8
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__MASK                          0x00000f00U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_13_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__SHIFT                                 12
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__MASK                         0x0000f000U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_13_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_14_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__SHIFT                                  16
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__MASK                          0x000f0000U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_14_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__SHIFT                                 20
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__MASK                         0x00f00000U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_14_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_15_data_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__SHIFT                                  24
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__WIDTH                                   4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__MASK                          0x0f000000U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__RESET                                   0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DATA_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_15_descr_qos */
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__SHIFT                                 28
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__WIDTH                                  4
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__MASK                         0xf0000000U
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__RESET                                  0
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__AXI_QOS_CFG_3__Q_15_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__AXI_QOS_CFG_3__TYPE                                            uint32_t
#define EMAC_REGS__AXI_QOS_CFG_3__READ                                         0xffffffffU
#define EMAC_REGS__AXI_QOS_CFG_3__WRITE                                        0xffffffffU

#endif /* __AXI_QOS_CFG_3_MACRO__ */


/* macros for axi_qos_cfg_3 */
#define EMAC_REGS__INST_AXI_QOS_CFG_3__NUM                                               1

/* macros for spec_add5_bottom */
#define EMAC_REGS__INST_SPEC_ADD5_BOTTOM__NUM                                            1

/* macros for spec_add5_top */
#define EMAC_REGS__INST_SPEC_ADD5_TOP__NUM                                               1

/* macros for spec_add6_bottom */
#define EMAC_REGS__INST_SPEC_ADD6_BOTTOM__NUM                                            1

/* macros for spec_add6_top */
#define EMAC_REGS__INST_SPEC_ADD6_TOP__NUM                                               1

/* macros for spec_add7_bottom */
#define EMAC_REGS__INST_SPEC_ADD7_BOTTOM__NUM                                            1

/* macros for spec_add7_top */
#define EMAC_REGS__INST_SPEC_ADD7_TOP__NUM                                               1

/* macros for spec_add8_bottom */
#define EMAC_REGS__INST_SPEC_ADD8_BOTTOM__NUM                                            1

/* macros for spec_add8_top */
#define EMAC_REGS__INST_SPEC_ADD8_TOP__NUM                                               1

/* macros for spec_add9_bottom */
#define EMAC_REGS__INST_SPEC_ADD9_BOTTOM__NUM                                            1

/* macros for spec_add9_top */
#define EMAC_REGS__INST_SPEC_ADD9_TOP__NUM                                               1

/* macros for spec_add10_bottom */
#define EMAC_REGS__INST_SPEC_ADD10_BOTTOM__NUM                                           1

/* macros for spec_add10_top */
#define EMAC_REGS__INST_SPEC_ADD10_TOP__NUM                                              1

/* macros for spec_add11_bottom */
#define EMAC_REGS__INST_SPEC_ADD11_BOTTOM__NUM                                           1

/* macros for spec_add11_top */
#define EMAC_REGS__INST_SPEC_ADD11_TOP__NUM                                              1

/* macros for spec_add12_bottom */
#define EMAC_REGS__INST_SPEC_ADD12_BOTTOM__NUM                                           1

/* macros for spec_add12_top */
#define EMAC_REGS__INST_SPEC_ADD12_TOP__NUM                                              1

/* macros for spec_add13_bottom */
#define EMAC_REGS__INST_SPEC_ADD13_BOTTOM__NUM                                           1

/* macros for spec_add13_top */
#define EMAC_REGS__INST_SPEC_ADD13_TOP__NUM                                              1

/* macros for spec_add14_bottom */
#define EMAC_REGS__INST_SPEC_ADD14_BOTTOM__NUM                                           1

/* macros for spec_add14_top */
#define EMAC_REGS__INST_SPEC_ADD14_TOP__NUM                                              1

/* macros for spec_add15_bottom */
#define EMAC_REGS__INST_SPEC_ADD15_BOTTOM__NUM                                           1

/* macros for spec_add15_top */
#define EMAC_REGS__INST_SPEC_ADD15_TOP__NUM                                              1

/* macros for spec_add16_bottom */
#define EMAC_REGS__INST_SPEC_ADD16_BOTTOM__NUM                                           1

/* macros for spec_add16_top */
#define EMAC_REGS__INST_SPEC_ADD16_TOP__NUM                                              1

/* macros for spec_add17_bottom */
#define EMAC_REGS__INST_SPEC_ADD17_BOTTOM__NUM                                           1

/* macros for spec_add17_top */
#define EMAC_REGS__INST_SPEC_ADD17_TOP__NUM                                              1

/* macros for spec_add18_bottom */
#define EMAC_REGS__INST_SPEC_ADD18_BOTTOM__NUM                                           1

/* macros for spec_add18_top */
#define EMAC_REGS__INST_SPEC_ADD18_TOP__NUM                                              1

/* macros for spec_add19_bottom */
#define EMAC_REGS__INST_SPEC_ADD19_BOTTOM__NUM                                           1

/* macros for spec_add19_top */
#define EMAC_REGS__INST_SPEC_ADD19_TOP__NUM                                              1

/* macros for spec_add20_bottom */
#define EMAC_REGS__INST_SPEC_ADD20_BOTTOM__NUM                                           1

/* macros for spec_add20_top */
#define EMAC_REGS__INST_SPEC_ADD20_TOP__NUM                                              1

/* macros for spec_add21_bottom */
#define EMAC_REGS__INST_SPEC_ADD21_BOTTOM__NUM                                           1

/* macros for spec_add21_top */
#define EMAC_REGS__INST_SPEC_ADD21_TOP__NUM                                              1

/* macros for spec_add22_bottom */
#define EMAC_REGS__INST_SPEC_ADD22_BOTTOM__NUM                                           1

/* macros for spec_add22_top */
#define EMAC_REGS__INST_SPEC_ADD22_TOP__NUM                                              1

/* macros for spec_add23_bottom */
#define EMAC_REGS__INST_SPEC_ADD23_BOTTOM__NUM                                           1

/* macros for spec_add23_top */
#define EMAC_REGS__INST_SPEC_ADD23_TOP__NUM                                              1

/* macros for spec_add24_bottom */
#define EMAC_REGS__INST_SPEC_ADD24_BOTTOM__NUM                                           1

/* macros for spec_add24_top */
#define EMAC_REGS__INST_SPEC_ADD24_TOP__NUM                                              1

/* macros for spec_add25_bottom */
#define EMAC_REGS__INST_SPEC_ADD25_BOTTOM__NUM                                           1

/* macros for spec_add25_top */
#define EMAC_REGS__INST_SPEC_ADD25_TOP__NUM                                              1

/* macros for spec_add26_bottom */
#define EMAC_REGS__INST_SPEC_ADD26_BOTTOM__NUM                                           1

/* macros for spec_add26_top */
#define EMAC_REGS__INST_SPEC_ADD26_TOP__NUM                                              1

/* macros for spec_add27_bottom */
#define EMAC_REGS__INST_SPEC_ADD27_BOTTOM__NUM                                           1

/* macros for spec_add27_top */
#define EMAC_REGS__INST_SPEC_ADD27_TOP__NUM                                              1

/* macros for spec_add28_bottom */
#define EMAC_REGS__INST_SPEC_ADD28_BOTTOM__NUM                                           1

/* macros for spec_add28_top */
#define EMAC_REGS__INST_SPEC_ADD28_TOP__NUM                                              1

/* macros for spec_add29_bottom */
#define EMAC_REGS__INST_SPEC_ADD29_BOTTOM__NUM                                           1

/* macros for spec_add29_top */
#define EMAC_REGS__INST_SPEC_ADD29_TOP__NUM                                              1

/* macros for spec_add30_bottom */
#define EMAC_REGS__INST_SPEC_ADD30_BOTTOM__NUM                                           1

/* macros for spec_add30_top */
#define EMAC_REGS__INST_SPEC_ADD30_TOP__NUM                                              1

/* macros for spec_add31_bottom */
#define EMAC_REGS__INST_SPEC_ADD31_BOTTOM__NUM                                           1

/* macros for spec_add31_top */
#define EMAC_REGS__INST_SPEC_ADD31_TOP__NUM                                              1

/* macros for spec_add32_bottom */
#define EMAC_REGS__INST_SPEC_ADD32_BOTTOM__NUM                                           1

/* macros for spec_add32_top */
#define EMAC_REGS__INST_SPEC_ADD32_TOP__NUM                                              1

/* macros for spec_add33_bottom */
#define EMAC_REGS__INST_SPEC_ADD33_BOTTOM__NUM                                           1

/* macros for spec_add33_top */
#define EMAC_REGS__INST_SPEC_ADD33_TOP__NUM                                              1

/* macros for spec_add34_bottom */
#define EMAC_REGS__INST_SPEC_ADD34_BOTTOM__NUM                                           1

/* macros for spec_add34_top */
#define EMAC_REGS__INST_SPEC_ADD34_TOP__NUM                                              1

/* macros for spec_add35_bottom */
#define EMAC_REGS__INST_SPEC_ADD35_BOTTOM__NUM                                           1

/* macros for spec_add35_top */
#define EMAC_REGS__INST_SPEC_ADD35_TOP__NUM                                              1

/* macros for spec_add36_bottom */
#define EMAC_REGS__INST_SPEC_ADD36_BOTTOM__NUM                                           1

/* macros for spec_add36_top */
#define EMAC_REGS__INST_SPEC_ADD36_TOP__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status1 */
#ifndef __EMAC_REGS__INT_Q_STATUS1_MACRO__
#define __EMAC_REGS__INT_Q_STATUS1_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS1__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS1__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS1__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS1__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS1__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS1__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS1__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS1__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS1__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS1__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS1_MACRO__ */


/* macros for int_q1_status */
#define EMAC_REGS__INST_INT_Q1_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status2 */
#ifndef __EMAC_REGS__INT_Q_STATUS2_MACRO__
#define __EMAC_REGS__INT_Q_STATUS2_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS2__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS2__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS2__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS2__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS2__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS2__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS2__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS2__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS2__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS2__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS2_MACRO__ */


/* macros for int_q2_status */
#define EMAC_REGS__INST_INT_Q2_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status3 */
#ifndef __EMAC_REGS__INT_Q_STATUS3_MACRO__
#define __EMAC_REGS__INT_Q_STATUS3_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS3__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS3__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS3__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS3__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS3__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS3__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS3__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS3__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS3__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS3__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS3_MACRO__ */


/* macros for int_q3_status */
#define EMAC_REGS__INST_INT_Q3_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status4 */
#ifndef __EMAC_REGS__INT_Q_STATUS4_MACRO__
#define __EMAC_REGS__INT_Q_STATUS4_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS4__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS4__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS4__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS4__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS4__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS4__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS4__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS4__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS4__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS4__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS4_MACRO__ */


/* macros for int_q4_status */
#define EMAC_REGS__INST_INT_Q4_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status5 */
#ifndef __EMAC_REGS__INT_Q_STATUS5_MACRO__
#define __EMAC_REGS__INT_Q_STATUS5_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS5__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS5__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS5__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS5__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS5__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS5__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS5__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS5__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS5__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS5__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS5_MACRO__ */


/* macros for int_q5_status */
#define EMAC_REGS__INST_INT_Q5_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status6 */
#ifndef __EMAC_REGS__INT_Q_STATUS6_MACRO__
#define __EMAC_REGS__INT_Q_STATUS6_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS6__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS6__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS6__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS6__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS6__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS6__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS6__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS6__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS6__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS6__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS6_MACRO__ */


/* macros for int_q6_status */
#define EMAC_REGS__INST_INT_Q6_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status7 */
#ifndef __EMAC_REGS__INT_Q_STATUS7_MACRO__
#define __EMAC_REGS__INT_Q_STATUS7_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS7__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS7__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS7__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS7__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS7__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS7__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS7__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS7__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS7__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS7__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS7_MACRO__ */


/* macros for int_q7_status */
#define EMAC_REGS__INST_INT_Q7_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status8 */
#ifndef __EMAC_REGS__INT_Q_STATUS8_MACRO__
#define __EMAC_REGS__INT_Q_STATUS8_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS8__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS8__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS8__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS8__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS8__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS8__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS8__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS8__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS8__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS8__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS8_MACRO__ */


/* macros for int_q8_status */
#define EMAC_REGS__INST_INT_Q8_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status9 */
#ifndef __EMAC_REGS__INT_Q_STATUS9_MACRO__
#define __EMAC_REGS__INT_Q_STATUS9_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__SHIFT                                1
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__MASK                       0x00000002U
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__RESET                                0
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS9__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__SHIFT                                2
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__WIDTH                                1
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__MASK                       0x00000004U
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__RESET                                0
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS9__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__SHIFT                          3
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__WIDTH                          1
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__MASK                 0x00000008U
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__RESET                          0
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT          5
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH          1
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK 0x00000020U
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET          0
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS9__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__SHIFT                                      6
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__WIDTH                                      1
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__MASK                             0x00000040U
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__RESET                                      0
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS9__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__SHIFT                               7
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__MASK                      0x00000080U
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS9__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__SHIFT                                    11
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__MASK                            0x00000800U
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__RESET                                   0b0
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS9__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS9__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS9__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_STATUS9__READ                                         0xffffffffU
#define EMAC_REGS__INT_Q_STATUS9__RCLR                                         0x000008eeU

#endif /* __INT_Q_STATUS9_MACRO__ */


/* macros for int_q9_status */
#define EMAC_REGS__INST_INT_Q9_STATUS__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_status10 */
#ifndef __EMAC_REGS__INT_Q_STATUS10_MACRO__
#define __EMAC_REGS__INT_Q_STATUS10_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS10__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS10__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS10__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS10__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS10__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS10__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS10__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS10__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS10__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS10__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS10_MACRO__ */


/* macros for int_q10_status */
#define EMAC_REGS__INST_INT_Q10_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status11 */
#ifndef __EMAC_REGS__INT_Q_STATUS11_MACRO__
#define __EMAC_REGS__INT_Q_STATUS11_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS11__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS11__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS11__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS11__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS11__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS11__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS11__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS11__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS11__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS11__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS11_MACRO__ */


/* macros for int_q11_status */
#define EMAC_REGS__INST_INT_Q11_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status12 */
#ifndef __EMAC_REGS__INT_Q_STATUS12_MACRO__
#define __EMAC_REGS__INT_Q_STATUS12_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS12__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS12__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS12__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS12__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS12__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS12__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS12__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS12__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS12__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS12__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS12_MACRO__ */


/* macros for int_q12_status */
#define EMAC_REGS__INST_INT_Q12_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status13 */
#ifndef __EMAC_REGS__INT_Q_STATUS13_MACRO__
#define __EMAC_REGS__INT_Q_STATUS13_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS13__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS13__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS13__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS13__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS13__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS13__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS13__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS13__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS13__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS13__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS13_MACRO__ */


/* macros for int_q13_status */
#define EMAC_REGS__INST_INT_Q13_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status14 */
#ifndef __EMAC_REGS__INT_Q_STATUS14_MACRO__
#define __EMAC_REGS__INT_Q_STATUS14_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS14__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS14__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS14__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS14__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS14__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS14__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS14__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS14__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS14__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS14__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS14_MACRO__ */


/* macros for int_q14_status */
#define EMAC_REGS__INST_INT_Q14_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_status15 */
#ifndef __EMAC_REGS__INT_Q_STATUS15_MACRO__
#define __EMAC_REGS__INT_Q_STATUS15_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__SHIFT                                     0
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__MASK                            0x00000001U
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete */
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__SHIFT                               1
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__MASK                      0x00000002U
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__RESET                               0
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_STATUS15__RECEIVE_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__SHIFT                               2
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__WIDTH                               1
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__MASK                      0x00000004U
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__RESET                               0
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_STATUS15__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read */
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__SHIFT                         3
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__WIDTH                         1
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__MASK                0x00000008U
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__RESET                         0
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__SHIFT                                     4
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__MASK                            0x00000010U
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision */
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT         5
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH         1
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET         0
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_STATUS15__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error */
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__SHIFT                                     6
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__WIDTH                                     1
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__MASK                            0x00000040U
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__RESET                                     0
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_STATUS15__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete */
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__SHIFT                              7
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__WIDTH                              1
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__MASK                     0x00000080U
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__RESET                              0
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_STATUS15__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_10_8__SHIFT                                  8
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_10_8__WIDTH                                  3
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_10_8__MASK                         0x00000700U
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_10_8__RESET                                  0
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok */
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__SHIFT                                   11
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__WIDTH                                    1
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__MASK                           0x00000800U
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__RESET                                  0b0
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_STATUS15__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_31_12__SHIFT                                12
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_31_12__WIDTH                                20
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_31_12__MASK                        0xfffff000U
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_31_12__RESET                                 0
#define EMAC_REGS__INT_Q_STATUS15__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_STATUS15__TYPE                                           uint32_t
#define EMAC_REGS__INT_Q_STATUS15__READ                                        0xffffffffU
#define EMAC_REGS__INT_Q_STATUS15__RCLR                                        0x000008eeU

#endif /* __INT_Q_STATUS15_MACRO__ */


/* macros for int_q15_status */
#define EMAC_REGS__INST_INT_Q15_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::transmit_qx_ptr */
#ifndef __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__
#define __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__

/* macros for field dma_tx_dis_q */
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SHIFT                                  0
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WIDTH                                  1
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MASK                         0x00000001U
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__RESET                                0b1
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_1 */
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__SHIFT                                    1
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__WIDTH                                    1
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__MASK                           0x00000002U
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__RESET                                  0b0
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_tx_q_ptr */
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__SHIFT                                  2
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WIDTH                                 30
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MASK                         0xfffffffcU
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__RESET                                  0
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0xfffffffcU)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffffcU) | (((uint32_t)(src) <<\
                    2) & 0xfffffffcU)
#define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0xfffffffcU)))
#define EMAC_REGS__TRANSMIT_QX_PTR__TYPE                                          uint32_t
#define EMAC_REGS__TRANSMIT_QX_PTR__READ                                       0xffffffffU
#define EMAC_REGS__TRANSMIT_QX_PTR__WRITE                                      0xffffffffU

#endif /* __TRANSMIT_QX_PTR_MACRO__ */


/* macros for transmit_q1_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q1_PTR__NUM                                             1

/* macros for transmit_q2_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q2_PTR__NUM                                             1

/* macros for transmit_q3_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q3_PTR__NUM                                             1

/* macros for transmit_q4_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q4_PTR__NUM                                             1

/* macros for transmit_q5_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q5_PTR__NUM                                             1

/* macros for transmit_q6_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q6_PTR__NUM                                             1

/* macros for transmit_q7_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q7_PTR__NUM                                             1

/* macros for transmit_q8_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q8_PTR__NUM                                             1

/* macros for transmit_q9_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q9_PTR__NUM                                             1

/* macros for transmit_q10_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q10_PTR__NUM                                            1

/* macros for transmit_q11_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q11_PTR__NUM                                            1

/* macros for transmit_q12_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q12_PTR__NUM                                            1

/* macros for transmit_q13_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q13_PTR__NUM                                            1

/* macros for transmit_q14_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q14_PTR__NUM                                            1

/* macros for transmit_q15_ptr */
#define EMAC_REGS__INST_TRANSMIT_Q15_PTR__NUM                                            1

/* macros for BlueprintGlobalNameSpace::receive_qx_ptr */
#ifndef __EMAC_REGS__RECEIVE_QX_PTR_MACRO__
#define __EMAC_REGS__RECEIVE_QX_PTR_MACRO__

/* macros for field dma_rx_dis_q */
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SHIFT                                   0
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WIDTH                                   1
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MASK                          0x00000001U
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__RESET                                 0b1
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__READ(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_1 */
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__SHIFT                                     1
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__WIDTH                                     1
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__MASK                            0x00000002U
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__RESET                                   0b0
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_rx_q_ptr */
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__SHIFT                                   2
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WIDTH                                  30
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MASK                          0xfffffffcU
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__RESET                                   0
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0xfffffffcU)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xfffffffcU) | (((uint32_t)(src) <<\
                    2) & 0xfffffffcU)
#define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0xfffffffcU)))
#define EMAC_REGS__RECEIVE_QX_PTR__TYPE                                           uint32_t
#define EMAC_REGS__RECEIVE_QX_PTR__READ                                        0xffffffffU
#define EMAC_REGS__RECEIVE_QX_PTR__WRITE                                       0xffffffffU

#endif /* __RECEIVE_QX_PTR_MACRO__ */


/* macros for receive_q1_ptr */
#define EMAC_REGS__INST_RECEIVE_Q1_PTR__NUM                                              1

/* macros for receive_q2_ptr */
#define EMAC_REGS__INST_RECEIVE_Q2_PTR__NUM                                              1

/* macros for receive_q3_ptr */
#define EMAC_REGS__INST_RECEIVE_Q3_PTR__NUM                                              1

/* macros for receive_q4_ptr */
#define EMAC_REGS__INST_RECEIVE_Q4_PTR__NUM                                              1

/* macros for receive_q5_ptr */
#define EMAC_REGS__INST_RECEIVE_Q5_PTR__NUM                                              1

/* macros for receive_q6_ptr */
#define EMAC_REGS__INST_RECEIVE_Q6_PTR__NUM                                              1

/* macros for receive_q7_ptr */
#define EMAC_REGS__INST_RECEIVE_Q7_PTR__NUM                                              1

/* macros for BlueprintGlobalNameSpace::dma_rxbuf_size_q */
#ifndef __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__
#define __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__

/* macros for field dma_rx_q_buf_size */
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__SHIFT                            0
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WIDTH                            8
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MASK                   0x000000ffU
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__RESET                            2
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__SHIFT                                8
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__WIDTH                               24
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__MASK                       0xffffff00U
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__RESET                                0
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__TYPE                                         uint32_t
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__READ                                      0xffffffffU
#define EMAC_REGS__DMA_RXBUF_SIZE_Q__WRITE                                     0xffffffffU

#endif /* __DMA_RXBUF_SIZE_Q_MACRO__ */


/* macros for dma_rxbuf_size_q1 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q1__NUM                                           1

/* macros for dma_rxbuf_size_q2 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q2__NUM                                           1

/* macros for dma_rxbuf_size_q3 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q3__NUM                                           1

/* macros for dma_rxbuf_size_q4 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q4__NUM                                           1

/* macros for dma_rxbuf_size_q5 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q5__NUM                                           1

/* macros for dma_rxbuf_size_q6 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q6__NUM                                           1

/* macros for dma_rxbuf_size_q7 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q7__NUM                                           1

/* macros for BlueprintGlobalNameSpace::cbs_control */
#ifndef __EMAC_REGS__CBS_CONTROL_MACRO__
#define __EMAC_REGS__CBS_CONTROL_MACRO__

/* macros for field cbs_enable_queue_a */
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SHIFT                                0
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WIDTH                                1
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MASK                       0x00000001U
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__RESET                                0
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field cbs_enable_queue_b */
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SHIFT                                1
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WIDTH                                1
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MASK                       0x00000002U
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__RESET                                0
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_31_2 */
#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__SHIFT                                     2
#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__WIDTH                                    30
#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__MASK                            0xfffffffcU
#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__RESET                                     0
#define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__CBS_CONTROL__TYPE                                              uint32_t
#define EMAC_REGS__CBS_CONTROL__READ                                           0xffffffffU
#define EMAC_REGS__CBS_CONTROL__WRITE                                          0xffffffffU

#endif /* __CBS_CONTROL_MACRO__ */


/* macros for cbs_control */
#define EMAC_REGS__INST_CBS_CONTROL__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::cbs_idleslope_q_a */
#ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__
#define __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__

/* macros for field idleslope_a */
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__SHIFT                                 0
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WIDTH                                32
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MASK                        0xffffffffU
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__RESET                                 0
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__TYPE                                        uint32_t
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__READ                                     0xffffffffU
#define EMAC_REGS__CBS_IDLESLOPE_Q_A__WRITE                                    0xffffffffU

#endif /* __CBS_IDLESLOPE_Q_A_MACRO__ */


/* macros for cbs_idleslope_q_a */
#define EMAC_REGS__INST_CBS_IDLESLOPE_Q_A__NUM                                           1

/* macros for BlueprintGlobalNameSpace::cbs_idleslope_q_b */
#ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__
#define __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__

/* macros for field idleslope_b */
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__SHIFT                                 0
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WIDTH                                32
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MASK                        0xffffffffU
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__RESET                                 0
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__TYPE                                        uint32_t
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__READ                                     0xffffffffU
#define EMAC_REGS__CBS_IDLESLOPE_Q_B__WRITE                                    0xffffffffU

#endif /* __CBS_IDLESLOPE_Q_B_MACRO__ */


/* macros for cbs_idleslope_q_b */
#define EMAC_REGS__INST_CBS_IDLESLOPE_Q_B__NUM                                           1

/* macros for BlueprintGlobalNameSpace::upper_tx_q_base_addr */
#ifndef __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__
#define __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__

/* macros for field upper_tx_q_base_addr */
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__SHIFT                     0
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WIDTH                    32
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MASK            0xffffffffU
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__RESET                     0
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__TYPE                                     uint32_t
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__READ                                  0xffffffffU
#define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__WRITE                                 0xffffffffU

#endif /* __UPPER_TX_Q_BASE_ADDR_MACRO__ */


/* macros for upper_tx_q_base_addr */
#define EMAC_REGS__INST_UPPER_TX_Q_BASE_ADDR__NUM                                        1

/* macros for BlueprintGlobalNameSpace::tx_bd_control */
#ifndef __EMAC_REGS__TX_BD_CONTROL_MACRO__
#define __EMAC_REGS__TX_BD_CONTROL_MACRO__

/* macros for field reserved_3_0 */
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__SHIFT                                    0
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__WIDTH                                    4
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__MASK                           0x0000000fU
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__RESET                                    0
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__READ(src)  ((uint32_t)(src) & 0x0000000fU)

/* macros for field tx_bd_ts_mode */
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__SHIFT                                   4
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WIDTH                                   2
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MASK                          0x00000030U
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__RESET                                   0
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000030U) >> 4)
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000030U)
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((uint32_t)(src) <<\
                    4) & 0x00000030U)
#define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field reserved_31_6 */
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__SHIFT                                   6
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__WIDTH                                  26
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__MASK                          0xffffffc0U
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__RESET                                   0
#define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__TX_BD_CONTROL__TYPE                                            uint32_t
#define EMAC_REGS__TX_BD_CONTROL__READ                                         0xffffffffU
#define EMAC_REGS__TX_BD_CONTROL__WRITE                                        0xffffffffU

#endif /* __TX_BD_CONTROL_MACRO__ */


/* macros for tx_bd_control */
#define EMAC_REGS__INST_TX_BD_CONTROL__NUM                                               1

/* macros for BlueprintGlobalNameSpace::rx_bd_control */
#ifndef __EMAC_REGS__RX_BD_CONTROL_MACRO__
#define __EMAC_REGS__RX_BD_CONTROL_MACRO__

/* macros for field reserved_3_0 */
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__SHIFT                                    0
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__WIDTH                                    4
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__MASK                           0x0000000fU
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__RESET                                    0
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__READ(src)  ((uint32_t)(src) & 0x0000000fU)

/* macros for field rx_bd_ts_mode */
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__SHIFT                                   4
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WIDTH                                   2
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MASK                          0x00000030U
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__RESET                                   0
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000030U) >> 4)
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000030U)
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((uint32_t)(src) <<\
                    4) & 0x00000030U)
#define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field reserved_31_6 */
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__SHIFT                                   6
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__WIDTH                                  26
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__MASK                          0xffffffc0U
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__RESET                                   0
#define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__RX_BD_CONTROL__TYPE                                            uint32_t
#define EMAC_REGS__RX_BD_CONTROL__READ                                         0xffffffffU
#define EMAC_REGS__RX_BD_CONTROL__WRITE                                        0xffffffffU

#endif /* __RX_BD_CONTROL_MACRO__ */


/* macros for rx_bd_control */
#define EMAC_REGS__INST_RX_BD_CONTROL__NUM                                               1

/* macros for BlueprintGlobalNameSpace::upper_rx_q_base_addr */
#ifndef __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__
#define __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__

/* macros for field upper_rx_q_base_addr */
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__SHIFT                     0
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WIDTH                    32
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MASK            0xffffffffU
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__RESET                     0
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__TYPE                                     uint32_t
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__READ                                  0xffffffffU
#define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__WRITE                                 0xffffffffU

#endif /* __UPPER_RX_Q_BASE_ADDR_MACRO__ */


/* macros for upper_rx_q_base_addr */
#define EMAC_REGS__INST_UPPER_RX_Q_BASE_ADDR__NUM                                        1

/* macros for BlueprintGlobalNameSpace::axi_host_arbitration */
#ifndef __EMAC_REGS__AXI_HOST_ARBITRATION_MACRO__
#define __EMAC_REGS__AXI_HOST_ARBITRATION_MACRO__

/* macros for field tx_data_prior */
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__SHIFT                            0
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__WIDTH                            1
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__MASK                   0x00000001U
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__RESET                            0
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DATA_PRIOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field tx_descr_prior */
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__SHIFT                           1
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__WIDTH                           1
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__MASK                  0x00000002U
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__RESET                           1
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TX_DESCR_PRIOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_descr_prior */
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__SHIFT                           2
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__WIDTH                           1
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__MASK                  0x00000004U
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__RESET                           0
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RX_DESCR_PRIOR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field reserved_3 */
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__SHIFT                               3
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__WIDTH                               1
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__MASK                      0x00000008U
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__RESET                             0b0
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field axi_read_arbiter */
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__SHIFT                         4
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__WIDTH                         3
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__MASK                0x00000070U
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__RESET                         0
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000070U) >> 4)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000070U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((uint32_t)(src) <<\
                    4) & 0x00000070U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_READ_ARBITER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field reserved_7 */
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__SHIFT                               7
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__WIDTH                               1
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__MASK                      0x00000080U
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__RESET                             0b0
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field axi_write_arbiter */
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__SHIFT                        8
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__WIDTH                        3
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__MASK               0x00000700U
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__RESET                        0
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000700U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((uint32_t)(src) <<\
                    8) & 0x00000700U)
#define EMAC_REGS__AXI_HOST_ARBITRATION__AXI_WRITE_ARBITER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field reserved_31_11 */
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_31_11__SHIFT                          11
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_31_11__WIDTH                          21
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_31_11__MASK                  0xfffff800U
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_31_11__RESET                           0
#define EMAC_REGS__AXI_HOST_ARBITRATION__RESERVED_31_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff800U) >> 11)
#define EMAC_REGS__AXI_HOST_ARBITRATION__TYPE                                     uint32_t
#define EMAC_REGS__AXI_HOST_ARBITRATION__READ                                  0xffffffffU
#define EMAC_REGS__AXI_HOST_ARBITRATION__WRITE                                 0xffffffffU

#endif /* __AXI_HOST_ARBITRATION_MACRO__ */


/* macros for axi_host_arbitration */
#define EMAC_REGS__INST_AXI_HOST_ARBITRATION__NUM                                        1

/* macros for BlueprintGlobalNameSpace::wd_counter */
#ifndef __EMAC_REGS__WD_COUNTER_MACRO__
#define __EMAC_REGS__WD_COUNTER_MACRO__

/* macros for field rx_bd_reread_timer */
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__SHIFT                                 0
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__WIDTH                                 4
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__MASK                        0x0000000fU
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__RESET                                 7
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__WD_COUNTER__RX_BD_REREAD_TIMER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field reserved_31_4 */
#define EMAC_REGS__WD_COUNTER__RESERVED_31_4__SHIFT                                      4
#define EMAC_REGS__WD_COUNTER__RESERVED_31_4__WIDTH                                     28
#define EMAC_REGS__WD_COUNTER__RESERVED_31_4__MASK                             0xfffffff0U
#define EMAC_REGS__WD_COUNTER__RESERVED_31_4__RESET                                      0
#define EMAC_REGS__WD_COUNTER__RESERVED_31_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffff0U) >> 4)
#define EMAC_REGS__WD_COUNTER__TYPE                                               uint32_t
#define EMAC_REGS__WD_COUNTER__READ                                            0xffffffffU
#define EMAC_REGS__WD_COUNTER__WRITE                                           0xffffffffU

#endif /* __WD_COUNTER_MACRO__ */


/* macros for wd_counter */
#define EMAC_REGS__INST_WD_COUNTER__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::axi_tx_full_thresh0 */
#ifndef __EMAC_REGS__AXI_TX_FULL_THRESH0_MACRO__
#define __EMAC_REGS__AXI_TX_FULL_THRESH0_MACRO__

/* macros for field axi_tx_full_adj_1 */
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__SHIFT                         0
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__WIDTH                         8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__MASK                0x000000ffU
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__RESET                         8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_1__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field reserved_15_8 */
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_15_8__SHIFT                             8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_15_8__WIDTH                             8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_15_8__MASK                    0x0000ff00U
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_15_8__RESET                             0
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_15_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field axi_tx_full_adj_0 */
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__SHIFT                        16
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__WIDTH                         8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__MASK                0x00ff0000U
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__RESET                         6
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__AXI_TX_FULL_ADJ_0__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field reserved_31_24 */
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_31_24__SHIFT                           24
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_31_24__WIDTH                            8
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_31_24__MASK                   0xff000000U
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_31_24__RESET                            0
#define EMAC_REGS__AXI_TX_FULL_THRESH0__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__AXI_TX_FULL_THRESH0__TYPE                                      uint32_t
#define EMAC_REGS__AXI_TX_FULL_THRESH0__READ                                   0xffffffffU
#define EMAC_REGS__AXI_TX_FULL_THRESH0__WRITE                                  0xffffffffU

#endif /* __AXI_TX_FULL_THRESH0_MACRO__ */


/* macros for axi_tx_full_thresh0 */
#define EMAC_REGS__INST_AXI_TX_FULL_THRESH0__NUM                                         1

/* macros for BlueprintGlobalNameSpace::axi_tx_full_thresh1 */
#ifndef __EMAC_REGS__AXI_TX_FULL_THRESH1_MACRO__
#define __EMAC_REGS__AXI_TX_FULL_THRESH1_MACRO__

/* macros for field axi_tx_full_adj_3 */
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__SHIFT                         0
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__WIDTH                         8
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__MASK                0x000000ffU
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__RESET                         0
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_3__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field reserved_15_8 */
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_15_8__SHIFT                             8
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_15_8__WIDTH                             8
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_15_8__MASK                    0x0000ff00U
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_15_8__RESET                             0
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_15_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field axi_tx_full_adj_2 */
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__SHIFT                        16
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__WIDTH                         8
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__MASK                0x00ff0000U
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__RESET                         0
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__AXI_TX_FULL_ADJ_2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field reserved_31_24 */
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_31_24__SHIFT                           24
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_31_24__WIDTH                            8
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_31_24__MASK                   0xff000000U
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_31_24__RESET                            0
#define EMAC_REGS__AXI_TX_FULL_THRESH1__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__AXI_TX_FULL_THRESH1__TYPE                                      uint32_t
#define EMAC_REGS__AXI_TX_FULL_THRESH1__READ                                   0xffffffffU
#define EMAC_REGS__AXI_TX_FULL_THRESH1__WRITE                                  0xffffffffU

#endif /* __AXI_TX_FULL_THRESH1_MACRO__ */


/* macros for axi_tx_full_thresh1 */
#define EMAC_REGS__INST_AXI_TX_FULL_THRESH1__NUM                                         1

/* macros for BlueprintGlobalNameSpace::screening_type_1_register */
#ifndef __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__
#define __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__

/* macros for field queue_number */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__SHIFT                        0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WIDTH                        4
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MASK               0x0000000fU
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__RESET                        0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field dstc_match */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__SHIFT                          4
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WIDTH                          8
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MASK                 0x00000ff0U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__RESET                          0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000ff0U) >> 4)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000ff0U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000ff0U) | (((uint32_t)(src) <<\
                    4) & 0x00000ff0U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000ff0U)))

/* macros for field udp_port_match */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__SHIFT                     12
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WIDTH                     16
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MASK             0x0ffff000U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__RESET                      0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0ffff000U) >> 12)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0ffff000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0ffff000U) | (((uint32_t)(src) <<\
                    12) & 0x0ffff000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0ffff000U)))

/* macros for field dstc_enable */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SHIFT                        28
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WIDTH                         1
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MASK                0x10000000U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__RESET                         0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field udp_port_match_enable */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SHIFT              29
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WIDTH               1
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MASK      0x20000000U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__RESET               0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field drop_on_match */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__SHIFT                      30
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__WIDTH                       1
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__MASK              0x40000000U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__RESET                       0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DROP_ON_MATCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field reserved_31 */
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__SHIFT                        31
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__WIDTH                         1
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__MASK                0x80000000U
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__RESET                         0
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__TYPE                                uint32_t
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__READ                             0xffffffffU
#define EMAC_REGS__SCREENING_TYPE_1_REGISTER__WRITE                            0xffffffffU

#endif /* __SCREENING_TYPE_1_REGISTER_MACRO__ */


/* macros for screening_type_1_register_0 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_0__NUM                                 1

/* macros for screening_type_1_register_1 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_1__NUM                                 1

/* macros for screening_type_1_register_2 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_2__NUM                                 1

/* macros for screening_type_1_register_3 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_3__NUM                                 1

/* macros for screening_type_1_register_4 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_4__NUM                                 1

/* macros for screening_type_1_register_5 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_5__NUM                                 1

/* macros for screening_type_1_register_6 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_6__NUM                                 1

/* macros for screening_type_1_register_7 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_7__NUM                                 1

/* macros for screening_type_1_register_8 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_8__NUM                                 1

/* macros for screening_type_1_register_9 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_9__NUM                                 1

/* macros for screening_type_1_register_10 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_10__NUM                                1

/* macros for screening_type_1_register_11 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_11__NUM                                1

/* macros for screening_type_1_register_12 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_12__NUM                                1

/* macros for screening_type_1_register_13 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_13__NUM                                1

/* macros for screening_type_1_register_14 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_14__NUM                                1

/* macros for screening_type_1_register_15 */
#define EMAC_REGS__INST_SCREENING_TYPE_1_REGISTER_15__NUM                                1

/* macros for BlueprintGlobalNameSpace::screening_type_2_register */
#ifndef __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__
#define __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__

/* macros for field queue_number */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__SHIFT                        0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WIDTH                        4
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MASK               0x0000000fU
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__RESET                        0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field vlan_priority */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__SHIFT                       4
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WIDTH                       3
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MASK              0x00000070U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__RESET                       0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000070U) >> 4)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000070U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((uint32_t)(src) <<\
                    4) & 0x00000070U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field reserved_7 */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SHIFT                          7
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WIDTH                          1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MASK                 0x00000080U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__RESET                          0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field vlan_enable */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SHIFT                         8
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WIDTH                         1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MASK                0x00000100U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__RESET                         0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field ethertype_reg_index */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__SHIFT                 9
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__WIDTH                 3
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__MASK        0x00000e00U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__RESET                 0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000e00U) >> 9)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000e00U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000e00U) | (((uint32_t)(src) <<\
                    9) & 0x00000e00U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_REG_INDEX__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000e00U)))

/* macros for field ethertype_enable */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SHIFT                   12
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WIDTH                    1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MASK           0x00001000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__RESET                    0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field compare_a */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__SHIFT                          13
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WIDTH                           5
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MASK                  0x0003e000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__RESET                           0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0003e000U) >> 13)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x0003e000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0003e000U) | (((uint32_t)(src) <<\
                    13) & 0x0003e000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x0003e000U)))

/* macros for field compare_a_enable */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SHIFT                   18
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WIDTH                    1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MASK           0x00040000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__RESET                    0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field compare_b */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__SHIFT                          19
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WIDTH                           5
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MASK                  0x00f80000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__RESET                           0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f80000U) >> 19)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00f80000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f80000U) | (((uint32_t)(src) <<\
                    19) & 0x00f80000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00f80000U)))

/* macros for field compare_b_enable */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SHIFT                   24
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WIDTH                    1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MASK           0x01000000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__RESET                    0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field compare_c */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__SHIFT                          25
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WIDTH                           5
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MASK                  0x3e000000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__RESET                           0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3e000000U) >> 25)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x3e000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3e000000U) | (((uint32_t)(src) <<\
                    25) & 0x3e000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x3e000000U)))

/* macros for field compare_c_enable */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SHIFT                   30
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WIDTH                    1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MASK           0x40000000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__RESET                    0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field drop_on_match */
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__SHIFT                      31
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__WIDTH                       1
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__MASK              0x80000000U
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__RESET                       0
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__DROP_ON_MATCH__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__TYPE                                uint32_t
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__READ                             0xffffffffU
#define EMAC_REGS__SCREENING_TYPE_2_REGISTER__WRITE                            0xffffffffU

#endif /* __SCREENING_TYPE_2_REGISTER_MACRO__ */


/* macros for screening_type_2_register_0 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_0__NUM                                 1

/* macros for screening_type_2_register_1 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_1__NUM                                 1

/* macros for screening_type_2_register_2 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_2__NUM                                 1

/* macros for screening_type_2_register_3 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_3__NUM                                 1

/* macros for screening_type_2_register_4 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_4__NUM                                 1

/* macros for screening_type_2_register_5 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_5__NUM                                 1

/* macros for screening_type_2_register_6 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_6__NUM                                 1

/* macros for screening_type_2_register_7 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_7__NUM                                 1

/* macros for screening_type_2_register_8 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_8__NUM                                 1

/* macros for screening_type_2_register_9 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_9__NUM                                 1

/* macros for screening_type_2_register_10 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_10__NUM                                1

/* macros for screening_type_2_register_11 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_11__NUM                                1

/* macros for screening_type_2_register_12 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_12__NUM                                1

/* macros for screening_type_2_register_13 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_13__NUM                                1

/* macros for screening_type_2_register_14 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_14__NUM                                1

/* macros for screening_type_2_register_15 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_REGISTER_15__NUM                                1

/* macros for BlueprintGlobalNameSpace::tx_sched_ctrl */
#ifndef __EMAC_REGS__TX_SCHED_CTRL_MACRO__
#define __EMAC_REGS__TX_SCHED_CTRL_MACRO__

/* macros for field tx_sched_q0 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__SHIFT                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__MASK                            0x00000003U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__READ(src)   ((uint32_t)(src) & 0x00000003U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__WRITE(src)  ((uint32_t)(src) & 0x00000003U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((uint32_t)(src) &\
                    0x00000003U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q0__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000003U)))

/* macros for field tx_sched_q1 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__SHIFT                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MASK                            0x0000000cU
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000000cU) >> 2)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x0000000cU)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000cU) | (((uint32_t)(src) <<\
                    2) & 0x0000000cU)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x0000000cU)))

/* macros for field tx_sched_q2 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__SHIFT                                     4
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MASK                            0x00000030U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000030U) >> 4)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000030U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000030U) | (((uint32_t)(src) <<\
                    4) & 0x00000030U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000030U)))

/* macros for field tx_sched_q3 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__SHIFT                                     6
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MASK                            0x000000c0U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000c0U) >> 6)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x000000c0U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000c0U) | (((uint32_t)(src) <<\
                    6) & 0x000000c0U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x000000c0U)))

/* macros for field tx_sched_q4 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__SHIFT                                     8
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MASK                            0x00000300U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000300U) >> 8)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000300U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000300U) | (((uint32_t)(src) <<\
                    8) & 0x00000300U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000300U)))

/* macros for field tx_sched_q5 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__SHIFT                                    10
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MASK                            0x00000c00U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000c00U) >> 10)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000c00U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000c00U) | (((uint32_t)(src) <<\
                    10) & 0x00000c00U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000c00U)))

/* macros for field tx_sched_q6 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__SHIFT                                    12
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MASK                            0x00003000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00003000U) >> 12)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00003000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((uint32_t)(src) <<\
                    12) & 0x00003000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field tx_sched_q7 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__SHIFT                                    14
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MASK                            0x0000c000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000c000U) >> 14)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x0000c000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000c000U) | (((uint32_t)(src) <<\
                    14) & 0x0000c000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x0000c000U)))

/* macros for field tx_sched_q8 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__SHIFT                                    16
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MASK                            0x00030000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00030000U) >> 16)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00030000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((uint32_t)(src) <<\
                    16) & 0x00030000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00030000U)))

/* macros for field tx_sched_q9 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__SHIFT                                    18
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WIDTH                                     2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MASK                            0x000c0000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__RESET                                     0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000c0000U) >> 18)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x000c0000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000c0000U) | (((uint32_t)(src) <<\
                    18) & 0x000c0000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x000c0000U)))

/* macros for field tx_sched_q10 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__SHIFT                                   20
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MASK                           0x00300000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00300000U) >> 20)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00300000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00300000U) | (((uint32_t)(src) <<\
                    20) & 0x00300000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00300000U)))

/* macros for field tx_sched_q11 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__SHIFT                                   22
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MASK                           0x00c00000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00c00000U) >> 22)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00c00000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00c00000U) | (((uint32_t)(src) <<\
                    22) & 0x00c00000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00c00000U)))

/* macros for field tx_sched_q12 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__SHIFT                                   24
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MASK                           0x03000000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x03000000U) >> 24)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x03000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03000000U) | (((uint32_t)(src) <<\
                    24) & 0x03000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x03000000U)))

/* macros for field tx_sched_q13 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__SHIFT                                   26
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MASK                           0x0c000000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0c000000U) >> 26)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x0c000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0c000000U) | (((uint32_t)(src) <<\
                    26) & 0x0c000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x0c000000U)))

/* macros for field tx_sched_q14 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__SHIFT                                   28
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MASK                           0x30000000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x30000000U) >> 28)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x30000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((uint32_t)(src) <<\
                    28) & 0x30000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field tx_sched_q15 */
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__SHIFT                                   30
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WIDTH                                    2
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MASK                           0xc0000000U
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__RESET                                    0
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__TX_SCHED_CTRL__TYPE                                            uint32_t
#define EMAC_REGS__TX_SCHED_CTRL__READ                                         0xffffffffU
#define EMAC_REGS__TX_SCHED_CTRL__WRITE                                        0xffffffffU

#endif /* __TX_SCHED_CTRL_MACRO__ */


/* macros for tx_sched_ctrl */
#define EMAC_REGS__INST_TX_SCHED_CTRL__NUM                                               1

/* macros for BlueprintGlobalNameSpace::bw_rate_limit_q0to3 */
#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__
#define __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__

/* macros for field dwrr_ets_weight_q0 */
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__SHIFT                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MASK               0x000000ffU
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field dwrr_ets_weight_q1 */
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__SHIFT                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MASK               0x0000ff00U
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field dwrr_ets_weight_q2 */
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__SHIFT                       16
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MASK               0x00ff0000U
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field dwrr_ets_weight_q3 */
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__SHIFT                       24
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MASK               0xff000000U
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__TYPE                                      uint32_t
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__READ                                   0xffffffffU
#define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__WRITE                                  0xffffffffU

#endif /* __BW_RATE_LIMIT_Q0TO3_MACRO__ */


/* macros for bw_rate_limit_q0to3 */
#define EMAC_REGS__INST_BW_RATE_LIMIT_Q0TO3__NUM                                         1

/* macros for BlueprintGlobalNameSpace::bw_rate_limit_q4to7 */
#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__
#define __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__

/* macros for field dwrr_ets_weight_q4 */
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__SHIFT                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MASK               0x000000ffU
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field dwrr_ets_weight_q5 */
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__SHIFT                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MASK               0x0000ff00U
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field dwrr_ets_weight_q6 */
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__SHIFT                       16
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MASK               0x00ff0000U
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field dwrr_ets_weight_q7 */
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__SHIFT                       24
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WIDTH                        8
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MASK               0xff000000U
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__RESET                        0
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__TYPE                                      uint32_t
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__READ                                   0xffffffffU
#define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__WRITE                                  0xffffffffU

#endif /* __BW_RATE_LIMIT_Q4TO7_MACRO__ */


/* macros for bw_rate_limit_q4to7 */
#define EMAC_REGS__INST_BW_RATE_LIMIT_Q4TO7__NUM                                         1

/* macros for BlueprintGlobalNameSpace::bw_rate_limit_q8to11 */
#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__
#define __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__

/* macros for field dwrr_ets_weight_q8 */
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__SHIFT                       0
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WIDTH                       8
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MASK              0x000000ffU
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__RESET                       0
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field dwrr_ets_weight_q9 */
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__SHIFT                       8
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WIDTH                       8
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MASK              0x0000ff00U
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__RESET                       0
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field dwrr_ets_weight_q10 */
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__SHIFT                     16
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WIDTH                      8
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MASK             0x00ff0000U
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__RESET                      0
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field dwrr_ets_weight_q11 */
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__SHIFT                     24
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WIDTH                      8
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MASK             0xff000000U
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__RESET                      0
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__TYPE                                     uint32_t
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__READ                                  0xffffffffU
#define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__WRITE                                 0xffffffffU

#endif /* __BW_RATE_LIMIT_Q8TO11_MACRO__ */


/* macros for bw_rate_limit_q8to11 */
#define EMAC_REGS__INST_BW_RATE_LIMIT_Q8TO11__NUM                                        1

/* macros for BlueprintGlobalNameSpace::bw_rate_limit_q12to15 */
#ifndef __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__
#define __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__

/* macros for field dwrr_ets_weight_q12 */
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__SHIFT                     0
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WIDTH                     8
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MASK            0x000000ffU
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__RESET                     0
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field dwrr_ets_weight_q13 */
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__SHIFT                     8
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WIDTH                     8
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MASK            0x0000ff00U
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__RESET                     0
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field dwrr_ets_weight_q14 */
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__SHIFT                    16
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WIDTH                     8
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MASK            0x00ff0000U
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__RESET                     0
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field dwrr_ets_weight_q15 */
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__SHIFT                    24
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WIDTH                     8
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MASK            0xff000000U
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__RESET                     0
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xff000000U) | (((uint32_t)(src) <<\
                    24) & 0xff000000U)
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0xff000000U)))
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__TYPE                                    uint32_t
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__READ                                 0xffffffffU
#define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__WRITE                                0xffffffffU

#endif /* __BW_RATE_LIMIT_Q12TO15_MACRO__ */


/* macros for bw_rate_limit_q12to15 */
#define EMAC_REGS__INST_BW_RATE_LIMIT_Q12TO15__NUM                                       1

/* macros for BlueprintGlobalNameSpace::tx_q_seg_alloc_q_lower */
#ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER_MACRO__
#define __EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER_MACRO__

/* macros for field segment_alloc_q0 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__SHIFT                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__MASK              0x00000007U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((uint32_t)(src) &\
                    0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q0__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000007U)))

/* macros for field reserved_3_3 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__SHIFT                           3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__WIDTH                           1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__MASK                  0x00000008U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__RESET                           0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_3_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field segment_alloc_q1 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__SHIFT                       4
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__MASK              0x00000070U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000070U) >> 4)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000070U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((uint32_t)(src) <<\
                    4) & 0x00000070U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field reserved_7_7 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__SHIFT                           7
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__WIDTH                           1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__MASK                  0x00000080U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__RESET                           0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_7_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field segment_alloc_q2 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__SHIFT                       8
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__MASK              0x00000700U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000700U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((uint32_t)(src) <<\
                    8) & 0x00000700U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field reserved_11_11 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__SHIFT                        11
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__MASK                0x00000800U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_11_11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field segment_alloc_q3 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__SHIFT                      12
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__MASK              0x00007000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00007000U) >> 12)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00007000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((uint32_t)(src) <<\
                    12) & 0x00007000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q3__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field reserved_15_15 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__SHIFT                        15
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__MASK                0x00008000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_15_15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field segment_alloc_q4 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__SHIFT                      16
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__MASK              0x00070000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00070000U) >> 16)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00070000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((uint32_t)(src) <<\
                    16) & 0x00070000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q4__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field reserved_19_19 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__SHIFT                        19
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__MASK                0x00080000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_19_19__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field segment_alloc_q5 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__SHIFT                      20
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__MASK              0x00700000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00700000U) >> 20)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00700000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((uint32_t)(src) <<\
                    20) & 0x00700000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q5__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field reserved_23_23 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__SHIFT                        23
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__MASK                0x00800000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_23_23__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field segment_alloc_q6 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__SHIFT                      24
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__MASK              0x07000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x07000000U) >> 24)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x07000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((uint32_t)(src) <<\
                    24) & 0x07000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q6__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field reserved_27_27 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__SHIFT                        27
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__MASK                0x08000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_27_27__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field segment_alloc_q7 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__SHIFT                      28
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__MASK              0x70000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x70000000U) >> 28)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x70000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x70000000U) | (((uint32_t)(src) <<\
                    28) & 0x70000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC_Q7__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x70000000U)))

/* macros for field reserved_31_31 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__SHIFT                        31
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__MASK                0x80000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_31__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__TYPE                                   uint32_t
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__READ                                0xffffffffU
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_LOWER__WRITE                               0xffffffffU

#endif /* __TX_Q_SEG_ALLOC_Q_LOWER_MACRO__ */


/* macros for tx_q_seg_alloc_q_lower */
#define EMAC_REGS__INST_TX_Q_SEG_ALLOC_Q_LOWER__NUM                                      1

/* macros for BlueprintGlobalNameSpace::tx_q_seg_alloc_q_upper */
#ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER_MACRO__
#define __EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER_MACRO__

/* macros for field segment_alloc_q8 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__SHIFT                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__MASK              0x00000007U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((uint32_t)(src) &\
                    0x00000007U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q8__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000007U)))

/* macros for field reserved_3_3 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__SHIFT                           3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__WIDTH                           1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__MASK                  0x00000008U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__RESET                           0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_3_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field segment_alloc_q9 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__SHIFT                       4
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__WIDTH                       3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__MASK              0x00000070U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__RESET                       0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000070U) >> 4)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000070U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000070U) | (((uint32_t)(src) <<\
                    4) & 0x00000070U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q9__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000070U)))

/* macros for field reserved_7_7 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__SHIFT                           7
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__WIDTH                           1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__MASK                  0x00000080U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__RESET                           0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_7_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field segment_alloc_q10 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__SHIFT                      8
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__MASK             0x00000700U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000700U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000700U) | (((uint32_t)(src) <<\
                    8) & 0x00000700U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000700U)))

/* macros for field reserved_11_11 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__SHIFT                        11
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__MASK                0x00000800U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_11_11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field segment_alloc_q11 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__SHIFT                     12
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__MASK             0x00007000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00007000U) >> 12)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00007000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00007000U) | (((uint32_t)(src) <<\
                    12) & 0x00007000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q11__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00007000U)))

/* macros for field reserved_15_15 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__SHIFT                        15
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__MASK                0x00008000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_15_15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field segment_alloc_q12 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__SHIFT                     16
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__MASK             0x00070000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00070000U) >> 16)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00070000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00070000U) | (((uint32_t)(src) <<\
                    16) & 0x00070000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q12__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00070000U)))

/* macros for field reserved_19_19 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__SHIFT                        19
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__MASK                0x00080000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_19_19__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field segment_alloc_q13 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__SHIFT                     20
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__MASK             0x00700000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00700000U) >> 20)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00700000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00700000U) | (((uint32_t)(src) <<\
                    20) & 0x00700000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q13__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00700000U)))

/* macros for field reserved_23_23 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__SHIFT                        23
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__MASK                0x00800000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_23_23__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field segment_alloc_q14 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__SHIFT                     24
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__MASK             0x07000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x07000000U) >> 24)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x07000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x07000000U) | (((uint32_t)(src) <<\
                    24) & 0x07000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q14__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x07000000U)))

/* macros for field reserved_27_27 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__SHIFT                        27
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__MASK                0x08000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_27_27__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field segment_alloc_q15 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__SHIFT                     28
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__WIDTH                      3
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__MASK             0x70000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__RESET                      0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x70000000U) >> 28)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x70000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x70000000U) | (((uint32_t)(src) <<\
                    28) & 0x70000000U)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__SEGMENT_ALLOC_Q15__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x70000000U)))

/* macros for field reserved_31_31 */
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__SHIFT                        31
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__WIDTH                         1
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__MASK                0x80000000U
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__RESET                         0
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__RESERVED_31_31__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__TYPE                                   uint32_t
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__READ                                0xffffffffU
#define EMAC_REGS__TX_Q_SEG_ALLOC_Q_UPPER__WRITE                               0xffffffffU

#endif /* __TX_Q_SEG_ALLOC_Q_UPPER_MACRO__ */


/* macros for tx_q_seg_alloc_q_upper */
#define EMAC_REGS__INST_TX_Q_SEG_ALLOC_Q_UPPER__NUM                                      1

/* macros for receive_q8_ptr */
#define EMAC_REGS__INST_RECEIVE_Q8_PTR__NUM                                              1

/* macros for receive_q9_ptr */
#define EMAC_REGS__INST_RECEIVE_Q9_PTR__NUM                                              1

/* macros for receive_q10_ptr */
#define EMAC_REGS__INST_RECEIVE_Q10_PTR__NUM                                             1

/* macros for receive_q11_ptr */
#define EMAC_REGS__INST_RECEIVE_Q11_PTR__NUM                                             1

/* macros for receive_q12_ptr */
#define EMAC_REGS__INST_RECEIVE_Q12_PTR__NUM                                             1

/* macros for receive_q13_ptr */
#define EMAC_REGS__INST_RECEIVE_Q13_PTR__NUM                                             1

/* macros for receive_q14_ptr */
#define EMAC_REGS__INST_RECEIVE_Q14_PTR__NUM                                             1

/* macros for receive_q15_ptr */
#define EMAC_REGS__INST_RECEIVE_Q15_PTR__NUM                                             1

/* macros for dma_rxbuf_size_q8 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q8__NUM                                           1

/* macros for dma_rxbuf_size_q9 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q9__NUM                                           1

/* macros for dma_rxbuf_size_q10 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q10__NUM                                          1

/* macros for dma_rxbuf_size_q11 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q11__NUM                                          1

/* macros for dma_rxbuf_size_q12 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q12__NUM                                          1

/* macros for dma_rxbuf_size_q13 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q13__NUM                                          1

/* macros for dma_rxbuf_size_q14 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q14__NUM                                          1

/* macros for dma_rxbuf_size_q15 */
#define EMAC_REGS__INST_DMA_RXBUF_SIZE_Q15__NUM                                          1

/* macros for BlueprintGlobalNameSpace::int_q_enable */
#ifndef __EMAC_REGS__INT_Q_ENABLE_MACRO__
#define __EMAC_REGS__INT_Q_ENABLE_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SHIFT                                       0
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__WIDTH                                       1
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__MASK                              0x00000001U
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__RESET                                       0
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__READ(src)     ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field enable_receive_complete_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT                1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK       0x00000002U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET                0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field enable_rx_used_bit_read_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT                2
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH                1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MASK       0x00000004U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__RESET                0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field enable_transmit_used_bit_read_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT          3
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH          1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK 0x00000008U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET          0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__SHIFT                                       4
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__WIDTH                                       1
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__MASK                              0x00000010U
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__RESET                                       0
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
                    5
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
                    6
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
                    0x00000040U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field enable_transmit_complete_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT               7
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH               1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK      0x00000080U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET               0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__SHIFT                                    8
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__WIDTH                                    3
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__MASK                           0x00000700U
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__RESET                                    0
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field enable_resp_not_ok_interrupt */
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT                    11
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH                     1
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK            0x00000800U
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET                     0
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__SHIFT                                  12
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__WIDTH                                  20
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__MASK                          0xfffff000U
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__RESET                                   0
#define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_ENABLE__TYPE                                             uint32_t
#define EMAC_REGS__INT_Q_ENABLE__READ                                          0xfffff711U
#define EMAC_REGS__INT_Q_ENABLE__WRITE                                         0xfffff711U

#endif /* __INT_Q_ENABLE_MACRO__ */


/* macros for int_q1_enable */
#define EMAC_REGS__INST_INT_Q1_ENABLE__NUM                                               1

/* macros for int_q2_enable */
#define EMAC_REGS__INST_INT_Q2_ENABLE__NUM                                               1

/* macros for int_q3_enable */
#define EMAC_REGS__INST_INT_Q3_ENABLE__NUM                                               1

/* macros for int_q4_enable */
#define EMAC_REGS__INST_INT_Q4_ENABLE__NUM                                               1

/* macros for int_q5_enable */
#define EMAC_REGS__INST_INT_Q5_ENABLE__NUM                                               1

/* macros for int_q6_enable */
#define EMAC_REGS__INST_INT_Q6_ENABLE__NUM                                               1

/* macros for int_q7_enable */
#define EMAC_REGS__INST_INT_Q7_ENABLE__NUM                                               1

/* macros for BlueprintGlobalNameSpace::int_q_disable */
#ifndef __EMAC_REGS__INT_Q_DISABLE_MACRO__
#define __EMAC_REGS__INT_Q_DISABLE_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SHIFT                                      0
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__WIDTH                                      1
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__MASK                             0x00000001U
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__RESET                                      0
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__READ(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field disable_receive_complete_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT              1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK     0x00000002U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET              0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field disable_rx_used_bit_read_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT              2
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH              1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MASK     0x00000004U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__RESET              0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field disable_transmit_used_bit_read_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT        3
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH        1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK \
                    0x00000008U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET        0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__SHIFT                                      4
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__WIDTH                                      1
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__MASK                             0x00000010U
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__RESET                                      0
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
                    5
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
                    6
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
                    1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
                    0x00000040U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
                    0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field disable_transmit_complete_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT             7
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH             1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK    0x00000080U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET             0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__SHIFT                                   8
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__WIDTH                                   3
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__MASK                          0x00000700U
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__RESET                                   0
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field disable_resp_not_ok_interrupt */
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT                  11
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH                   1
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK          0x00000800U
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET                   0
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__SHIFT                                 12
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__WIDTH                                 20
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__MASK                         0xfffff000U
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__RESET                                  0
#define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_DISABLE__TYPE                                            uint32_t
#define EMAC_REGS__INT_Q_DISABLE__READ                                         0xfffff711U
#define EMAC_REGS__INT_Q_DISABLE__WRITE                                        0xfffff711U

#endif /* __INT_Q_DISABLE_MACRO__ */


/* macros for int_q1_disable */
#define EMAC_REGS__INST_INT_Q1_DISABLE__NUM                                              1

/* macros for int_q2_disable */
#define EMAC_REGS__INST_INT_Q2_DISABLE__NUM                                              1

/* macros for int_q3_disable */
#define EMAC_REGS__INST_INT_Q3_DISABLE__NUM                                              1

/* macros for int_q4_disable */
#define EMAC_REGS__INST_INT_Q4_DISABLE__NUM                                              1

/* macros for int_q5_disable */
#define EMAC_REGS__INST_INT_Q5_DISABLE__NUM                                              1

/* macros for int_q6_disable */
#define EMAC_REGS__INST_INT_Q6_DISABLE__NUM                                              1

/* macros for int_q7_disable */
#define EMAC_REGS__INST_INT_Q7_DISABLE__NUM                                              1

/* macros for BlueprintGlobalNameSpace::int_q_mask */
#ifndef __EMAC_REGS__INT_Q_MASK_MACRO__
#define __EMAC_REGS__INT_Q_MASK_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__SHIFT                                         0
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__WIDTH                                         1
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__MASK                                0x00000001U
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__RESET                                         0
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__READ(src)       ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__INT_Q_MASK__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field receive_complete_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT                    1
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH                    1
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK           0x00000002U
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET                    1
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_used_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SHIFT                             2
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__WIDTH                             1
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__MASK                    0x00000004U
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__RESET                             1
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field transmit_used_bit_read_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SHIFT              3
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__WIDTH              1
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__MASK     0x00000008U
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__RESET              0
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_4 */
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__SHIFT                                         4
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__WIDTH                                         1
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__MASK                                0x00000010U
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__RESET                                         0
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__INT_Q_MASK__RESERVED_4__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field retry_limit_exceeded_or_late_collision_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SHIFT \
                    5
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__WIDTH \
                    1
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__MASK \
                    0x00000020U
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__RESET \
                    1
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field amba_error_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT                          6
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH                          1
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK                 0x00000040U
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET                          1
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field transmit_complete_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT                   7
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH                   1
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK          0x00000080U
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET                   1
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_10_8 */
#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__SHIFT                                      8
#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__WIDTH                                      3
#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__MASK                             0x00000700U
#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__RESET                                      0
#define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000700U) >> 8)

/* macros for field resp_not_ok_interrupt_mask */
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT                        11
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH                         1
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK                0x00000800U
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET                         1
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field reserved_31_12 */
#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__SHIFT                                    12
#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__WIDTH                                    20
#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__MASK                            0xfffff000U
#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__RESET                                     0
#define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__INT_Q_MASK__TYPE                                               uint32_t
#define EMAC_REGS__INT_Q_MASK__READ                                            0xfffffff7U
#define EMAC_REGS__INT_Q_MASK__WRITE                                           0xfffffff7U

#endif /* __INT_Q_MASK_MACRO__ */


/* macros for int_q1_mask */
#define EMAC_REGS__INST_INT_Q1_MASK__NUM                                                 1

/* macros for int_q2_mask */
#define EMAC_REGS__INST_INT_Q2_MASK__NUM                                                 1

/* macros for int_q3_mask */
#define EMAC_REGS__INST_INT_Q3_MASK__NUM                                                 1

/* macros for int_q4_mask */
#define EMAC_REGS__INST_INT_Q4_MASK__NUM                                                 1

/* macros for int_q5_mask */
#define EMAC_REGS__INST_INT_Q5_MASK__NUM                                                 1

/* macros for int_q6_mask */
#define EMAC_REGS__INST_INT_Q6_MASK__NUM                                                 1

/* macros for int_q7_mask */
#define EMAC_REGS__INST_INT_Q7_MASK__NUM                                                 1

/* macros for int_q8_enable */
#define EMAC_REGS__INST_INT_Q8_ENABLE__NUM                                               1

/* macros for int_q9_enable */
#define EMAC_REGS__INST_INT_Q9_ENABLE__NUM                                               1

/* macros for int_q10_enable */
#define EMAC_REGS__INST_INT_Q10_ENABLE__NUM                                              1

/* macros for int_q11_enable */
#define EMAC_REGS__INST_INT_Q11_ENABLE__NUM                                              1

/* macros for int_q12_enable */
#define EMAC_REGS__INST_INT_Q12_ENABLE__NUM                                              1

/* macros for int_q13_enable */
#define EMAC_REGS__INST_INT_Q13_ENABLE__NUM                                              1

/* macros for int_q14_enable */
#define EMAC_REGS__INST_INT_Q14_ENABLE__NUM                                              1

/* macros for int_q15_enable */
#define EMAC_REGS__INST_INT_Q15_ENABLE__NUM                                              1

/* macros for int_q8_disable */
#define EMAC_REGS__INST_INT_Q8_DISABLE__NUM                                              1

/* macros for int_q9_disable */
#define EMAC_REGS__INST_INT_Q9_DISABLE__NUM                                              1

/* macros for int_q10_disable */
#define EMAC_REGS__INST_INT_Q10_DISABLE__NUM                                             1

/* macros for int_q11_disable */
#define EMAC_REGS__INST_INT_Q11_DISABLE__NUM                                             1

/* macros for int_q12_disable */
#define EMAC_REGS__INST_INT_Q12_DISABLE__NUM                                             1

/* macros for int_q13_disable */
#define EMAC_REGS__INST_INT_Q13_DISABLE__NUM                                             1

/* macros for int_q14_disable */
#define EMAC_REGS__INST_INT_Q14_DISABLE__NUM                                             1

/* macros for int_q15_disable */
#define EMAC_REGS__INST_INT_Q15_DISABLE__NUM                                             1

/* macros for int_q8_mask */
#define EMAC_REGS__INST_INT_Q8_MASK__NUM                                                 1

/* macros for int_q9_mask */
#define EMAC_REGS__INST_INT_Q9_MASK__NUM                                                 1

/* macros for int_q10_mask */
#define EMAC_REGS__INST_INT_Q10_MASK__NUM                                                1

/* macros for int_q11_mask */
#define EMAC_REGS__INST_INT_Q11_MASK__NUM                                                1

/* macros for int_q12_mask */
#define EMAC_REGS__INST_INT_Q12_MASK__NUM                                                1

/* macros for int_q13_mask */
#define EMAC_REGS__INST_INT_Q13_MASK__NUM                                                1

/* macros for int_q14_mask */
#define EMAC_REGS__INST_INT_Q14_MASK__NUM                                                1

/* macros for int_q15_mask */
#define EMAC_REGS__INST_INT_Q15_MASK__NUM                                                1

/* macros for BlueprintGlobalNameSpace::screening_type_2_ethertype_reg */
#ifndef __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__
#define __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__

/* macros for field compare_value */
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__SHIFT                  0
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WIDTH                 16
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MASK         0x0000ffffU
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__RESET                  0
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__SHIFT                16
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__WIDTH                16
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__MASK        0xffff0000U
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__RESET                 0
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__TYPE                           uint32_t
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__READ                        0xffffffffU
#define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__WRITE                       0xffffffffU

#endif /* __SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__ */


/* macros for screening_type_2_ethertype_reg_0 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_0__NUM                            1

/* macros for screening_type_2_ethertype_reg_1 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_1__NUM                            1

/* macros for screening_type_2_ethertype_reg_2 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_2__NUM                            1

/* macros for screening_type_2_ethertype_reg_3 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_3__NUM                            1

/* macros for screening_type_2_ethertype_reg_4 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_4__NUM                            1

/* macros for screening_type_2_ethertype_reg_5 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_5__NUM                            1

/* macros for screening_type_2_ethertype_reg_6 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_6__NUM                            1

/* macros for screening_type_2_ethertype_reg_7 */
#define EMAC_REGS__INST_SCREENING_TYPE_2_ETHERTYPE_REG_7__NUM                            1

/* macros for BlueprintGlobalNameSpace::type2_compare_word_0 */
#ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__
#define __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__

/* macros for field mask_value */
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__SHIFT                               0
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WIDTH                              16
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MASK                      0x0000ffffU
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__RESET                               0
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field compare_value */
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__SHIFT                           16
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WIDTH                           16
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MASK                   0xffff0000U
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__RESET                            0
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__TYPE                                     uint32_t
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__READ                                  0xffffffffU
#define EMAC_REGS__TYPE2_COMPARE_WORD_0__WRITE                                 0xffffffffU

#endif /* __TYPE2_COMPARE_WORD_0_MACRO__ */


/* macros for type2_compare_0_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_0_WORD_0__NUM                                      1

/* macros for BlueprintGlobalNameSpace::type2_compare_word_1 */
#ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__
#define __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__

/* macros for field offset_value */
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__SHIFT                             0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WIDTH                             7
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MASK                    0x0000007fU
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__RESET                             0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000007fU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000007fU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000007fU) | ((uint32_t)(src) &\
                    0x0000007fU)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000007fU)))

/* macros for field compare_offset */
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__SHIFT                           7
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WIDTH                           2
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MASK                  0x00000180U
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__RESET                           0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000180U) >> 7)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000180U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000180U) | (((uint32_t)(src) <<\
                    7) & 0x00000180U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000180U)))

/* macros for field disable_mask */
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SHIFT                             9
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WIDTH                             1
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MASK                    0x00000200U
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__RESET                             0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field compare_vlan_id */
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__SHIFT                         10
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__WIDTH                          1
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__MASK                 0x00000400U
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__RESET                          0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_VLAN_ID__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field reserved_31_11 */
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_11__SHIFT                          11
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_11__WIDTH                          21
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_11__MASK                  0xfffff800U
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_11__RESET                           0
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff800U) >> 11)
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__TYPE                                     uint32_t
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__READ                                  0xffffffffU
#define EMAC_REGS__TYPE2_COMPARE_WORD_1__WRITE                                 0xffffffffU

#endif /* __TYPE2_COMPARE_WORD_1_MACRO__ */


/* macros for type2_compare_0_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_0_WORD_1__NUM                                      1

/* macros for type2_compare_1_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_1_WORD_0__NUM                                      1

/* macros for type2_compare_1_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_1_WORD_1__NUM                                      1

/* macros for type2_compare_2_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_2_WORD_0__NUM                                      1

/* macros for type2_compare_2_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_2_WORD_1__NUM                                      1

/* macros for type2_compare_3_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_3_WORD_0__NUM                                      1

/* macros for type2_compare_3_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_3_WORD_1__NUM                                      1

/* macros for type2_compare_4_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_4_WORD_0__NUM                                      1

/* macros for type2_compare_4_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_4_WORD_1__NUM                                      1

/* macros for type2_compare_5_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_5_WORD_0__NUM                                      1

/* macros for type2_compare_5_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_5_WORD_1__NUM                                      1

/* macros for type2_compare_6_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_6_WORD_0__NUM                                      1

/* macros for type2_compare_6_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_6_WORD_1__NUM                                      1

/* macros for type2_compare_7_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_7_WORD_0__NUM                                      1

/* macros for type2_compare_7_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_7_WORD_1__NUM                                      1

/* macros for type2_compare_8_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_8_WORD_0__NUM                                      1

/* macros for type2_compare_8_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_8_WORD_1__NUM                                      1

/* macros for type2_compare_9_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_9_WORD_0__NUM                                      1

/* macros for type2_compare_9_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_9_WORD_1__NUM                                      1

/* macros for type2_compare_10_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_10_WORD_0__NUM                                     1

/* macros for type2_compare_10_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_10_WORD_1__NUM                                     1

/* macros for type2_compare_11_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_11_WORD_0__NUM                                     1

/* macros for type2_compare_11_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_11_WORD_1__NUM                                     1

/* macros for type2_compare_12_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_12_WORD_0__NUM                                     1

/* macros for type2_compare_12_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_12_WORD_1__NUM                                     1

/* macros for type2_compare_13_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_13_WORD_0__NUM                                     1

/* macros for type2_compare_13_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_13_WORD_1__NUM                                     1

/* macros for type2_compare_14_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_14_WORD_0__NUM                                     1

/* macros for type2_compare_14_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_14_WORD_1__NUM                                     1

/* macros for type2_compare_15_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_15_WORD_0__NUM                                     1

/* macros for type2_compare_15_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_15_WORD_1__NUM                                     1

/* macros for type2_compare_16_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_16_WORD_0__NUM                                     1

/* macros for type2_compare_16_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_16_WORD_1__NUM                                     1

/* macros for type2_compare_17_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_17_WORD_0__NUM                                     1

/* macros for type2_compare_17_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_17_WORD_1__NUM                                     1

/* macros for type2_compare_18_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_18_WORD_0__NUM                                     1

/* macros for type2_compare_18_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_18_WORD_1__NUM                                     1

/* macros for type2_compare_19_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_19_WORD_0__NUM                                     1

/* macros for type2_compare_19_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_19_WORD_1__NUM                                     1

/* macros for type2_compare_20_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_20_WORD_0__NUM                                     1

/* macros for type2_compare_20_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_20_WORD_1__NUM                                     1

/* macros for type2_compare_21_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_21_WORD_0__NUM                                     1

/* macros for type2_compare_21_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_21_WORD_1__NUM                                     1

/* macros for type2_compare_22_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_22_WORD_0__NUM                                     1

/* macros for type2_compare_22_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_22_WORD_1__NUM                                     1

/* macros for type2_compare_23_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_23_WORD_0__NUM                                     1

/* macros for type2_compare_23_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_23_WORD_1__NUM                                     1

/* macros for type2_compare_24_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_24_WORD_0__NUM                                     1

/* macros for type2_compare_24_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_24_WORD_1__NUM                                     1

/* macros for type2_compare_25_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_25_WORD_0__NUM                                     1

/* macros for type2_compare_25_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_25_WORD_1__NUM                                     1

/* macros for type2_compare_26_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_26_WORD_0__NUM                                     1

/* macros for type2_compare_26_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_26_WORD_1__NUM                                     1

/* macros for type2_compare_27_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_27_WORD_0__NUM                                     1

/* macros for type2_compare_27_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_27_WORD_1__NUM                                     1

/* macros for type2_compare_28_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_28_WORD_0__NUM                                     1

/* macros for type2_compare_28_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_28_WORD_1__NUM                                     1

/* macros for type2_compare_29_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_29_WORD_0__NUM                                     1

/* macros for type2_compare_29_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_29_WORD_1__NUM                                     1

/* macros for type2_compare_30_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_30_WORD_0__NUM                                     1

/* macros for type2_compare_30_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_30_WORD_1__NUM                                     1

/* macros for type2_compare_31_word_0 */
#define EMAC_REGS__INST_TYPE2_COMPARE_31_WORD_0__NUM                                     1

/* macros for type2_compare_31_word_1 */
#define EMAC_REGS__INST_TYPE2_COMPARE_31_WORD_1__NUM                                     1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q8 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q8_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q8_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__SHIFT                            0
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WIDTH                           30
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MASK                   0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__SHIFT                            30
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WIDTH                             2
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MASK                    0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__RESET                             0
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q8__TYPE                                       uint32_t
#define EMAC_REGS__ENST_START_TIME_Q8__READ                                    0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q8__WRITE                                   0xffffffffU

#endif /* __ENST_START_TIME_Q8_MACRO__ */


/* macros for enst_start_time_q8 */
#define EMAC_REGS__INST_ENST_START_TIME_Q8__NUM                                          1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q9 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q9_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q9_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__SHIFT                            0
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WIDTH                           30
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MASK                   0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__SHIFT                            30
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WIDTH                             2
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MASK                    0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__RESET                             0
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q9__TYPE                                       uint32_t
#define EMAC_REGS__ENST_START_TIME_Q9__READ                                    0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q9__WRITE                                   0xffffffffU

#endif /* __ENST_START_TIME_Q9_MACRO__ */


/* macros for enst_start_time_q9 */
#define EMAC_REGS__INST_ENST_START_TIME_Q9__NUM                                          1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q10 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q10_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q10_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q10__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q10__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q10__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q10_MACRO__ */


/* macros for enst_start_time_q10 */
#define EMAC_REGS__INST_ENST_START_TIME_Q10__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q11 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q11_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q11_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q11__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q11__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q11__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q11_MACRO__ */


/* macros for enst_start_time_q11 */
#define EMAC_REGS__INST_ENST_START_TIME_Q11__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q12 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q12_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q12_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q12__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q12__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q12__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q12_MACRO__ */


/* macros for enst_start_time_q12 */
#define EMAC_REGS__INST_ENST_START_TIME_Q12__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q13 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q13_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q13_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q13__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q13__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q13__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q13_MACRO__ */


/* macros for enst_start_time_q13 */
#define EMAC_REGS__INST_ENST_START_TIME_Q13__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q14 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q14_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q14_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q14__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q14__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q14__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q14_MACRO__ */


/* macros for enst_start_time_q14 */
#define EMAC_REGS__INST_ENST_START_TIME_Q14__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q15 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q15_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q15_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__SHIFT                           0
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WIDTH                          30
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MASK                  0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__RESET                           0
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__SHIFT                           30
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WIDTH                            2
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MASK                   0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q15__TYPE                                      uint32_t
#define EMAC_REGS__ENST_START_TIME_Q15__READ                                   0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q15__WRITE                                  0xffffffffU

#endif /* __ENST_START_TIME_Q15_MACRO__ */


/* macros for enst_start_time_q15 */
#define EMAC_REGS__INST_ENST_START_TIME_Q15__NUM                                         1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q8 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__SHIFT                                       0
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WIDTH                                      17
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MASK                              0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__RESET                                 0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__READ(src)     ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WRITE(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__SHIFT                               17
#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__WIDTH                               15
#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__MASK                       0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__RESET                                0
#define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q8__TYPE                                          uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q8__READ                                       0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q8__WRITE                                      0xffffffffU

#endif /* __ENST_ON_TIME_Q8_MACRO__ */


/* macros for enst_on_time_q8 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q8__NUM                                             1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q9 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__SHIFT                                       0
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WIDTH                                      17
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MASK                              0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__RESET                                 0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__READ(src)     ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WRITE(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__SHIFT                               17
#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__WIDTH                               15
#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__MASK                       0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__RESET                                0
#define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q9__TYPE                                          uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q9__READ                                       0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q9__WRITE                                      0xffffffffU

#endif /* __ENST_ON_TIME_Q9_MACRO__ */


/* macros for enst_on_time_q9 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q9__NUM                                             1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q10 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q10__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q10__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q10__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q10_MACRO__ */


/* macros for enst_on_time_q10 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q10__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q11 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q11__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q11__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q11__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q11_MACRO__ */


/* macros for enst_on_time_q11 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q11__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q12 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q12__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q12__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q12__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q12_MACRO__ */


/* macros for enst_on_time_q12 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q12__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q13 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q13__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q13__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q13__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q13_MACRO__ */


/* macros for enst_on_time_q13 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q13__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q14 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q14__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q14__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q14__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q14_MACRO__ */


/* macros for enst_on_time_q14 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q14__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q15 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__SHIFT                                      0
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WIDTH                                     17
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MASK                             0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__RESET                                0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__READ(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WRITE(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q15__TYPE                                         uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q15__READ                                      0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q15__WRITE                                     0xffffffffU

#endif /* __ENST_ON_TIME_Q15_MACRO__ */


/* macros for enst_on_time_q15 */
#define EMAC_REGS__INST_ENST_ON_TIME_Q15__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q8 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__SHIFT                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WIDTH                                    17
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MASK                            0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__RESET                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__READ(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WRITE(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q8__TYPE                                         uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q8__READ                                      0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q8__WRITE                                     0xffffffffU

#endif /* __ENST_OFF_TIME_Q8_MACRO__ */


/* macros for enst_off_time_q8 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q8__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q9 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__SHIFT                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WIDTH                                    17
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MASK                            0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__RESET                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__READ(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WRITE(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q9__TYPE                                         uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q9__READ                                      0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q9__WRITE                                     0xffffffffU

#endif /* __ENST_OFF_TIME_Q9_MACRO__ */


/* macros for enst_off_time_q9 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q9__NUM                                            1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q10 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q10__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q10__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q10__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q10_MACRO__ */


/* macros for enst_off_time_q10 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q10__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q11 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q11__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q11__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q11__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q11_MACRO__ */


/* macros for enst_off_time_q11 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q11__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q12 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q12__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q12__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q12__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q12_MACRO__ */


/* macros for enst_off_time_q12 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q12__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q13 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q13__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q13__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q13__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q13_MACRO__ */


/* macros for enst_off_time_q13 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q13__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q14 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q14__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q14__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q14__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q14_MACRO__ */


/* macros for enst_off_time_q14 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q14__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q15 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__SHIFT                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WIDTH                                   17
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MASK                           0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__RESET                                    0
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__READ(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WRITE(src) ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__RESET                              0
#define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q15__TYPE                                        uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q15__READ                                     0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q15__WRITE                                    0xffffffffU

#endif /* __ENST_OFF_TIME_Q15_MACRO__ */


/* macros for enst_off_time_q15 */
#define EMAC_REGS__INST_ENST_OFF_TIME_Q15__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_control */
#ifndef __EMAC_REGS__ENST_CONTROL_MACRO__
#define __EMAC_REGS__ENST_CONTROL_MACRO__

/* macros for field enst_enable_q8 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SHIFT                                   0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WIDTH                                   1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MASK                          0x00000001U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__RESET                                   0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__READ(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field enst_enable_q9 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SHIFT                                   1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WIDTH                                   1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MASK                          0x00000002U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__RESET                                   0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field enst_enable_q10 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SHIFT                                  2
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MASK                         0x00000004U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field enst_enable_q11 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SHIFT                                  3
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MASK                         0x00000008U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field enst_enable_q12 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SHIFT                                  4
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MASK                         0x00000010U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field enst_enable_q13 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SHIFT                                  5
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MASK                         0x00000020U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field enst_enable_q14 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SHIFT                                  6
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MASK                         0x00000040U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field enst_enable_q15 */
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SHIFT                                  7
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WIDTH                                  1
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MASK                         0x00000080U
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__RESET                                  0
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_31_8 */
#define EMAC_REGS__ENST_CONTROL__RESERVED_31_8__SHIFT                                    8
#define EMAC_REGS__ENST_CONTROL__RESERVED_31_8__WIDTH                                   24
#define EMAC_REGS__ENST_CONTROL__RESERVED_31_8__MASK                           0xffffff00U
#define EMAC_REGS__ENST_CONTROL__RESERVED_31_8__RESET                                    0
#define EMAC_REGS__ENST_CONTROL__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__ENST_CONTROL__TYPE                                             uint32_t
#define EMAC_REGS__ENST_CONTROL__READ                                          0xffffffffU
#define EMAC_REGS__ENST_CONTROL__WRITE                                         0xffffffffU

#endif /* __ENST_CONTROL_MACRO__ */


/* macros for enst_control */
#define EMAC_REGS__INST_ENST_CONTROL__NUM                                                1

/* macros for BlueprintGlobalNameSpace::frer_timeout */
#ifndef __EMAC_REGS__FRER_TIMEOUT_MACRO__
#define __EMAC_REGS__FRER_TIMEOUT_MACRO__

/* macros for field timeout */
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__SHIFT                                          0
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__WIDTH                                         16
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__MASK                                 0x0000ffffU
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__RESET                                          0
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__READ(src)        ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__WRITE(src)       ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__FRER_TIMEOUT__TIMEOUT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__FRER_TIMEOUT__RESERVED_31_16__SHIFT                                  16
#define EMAC_REGS__FRER_TIMEOUT__RESERVED_31_16__WIDTH                                  16
#define EMAC_REGS__FRER_TIMEOUT__RESERVED_31_16__MASK                          0xffff0000U
#define EMAC_REGS__FRER_TIMEOUT__RESERVED_31_16__RESET                                   0
#define EMAC_REGS__FRER_TIMEOUT__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__FRER_TIMEOUT__TYPE                                             uint32_t
#define EMAC_REGS__FRER_TIMEOUT__READ                                          0xffffffffU
#define EMAC_REGS__FRER_TIMEOUT__WRITE                                         0xffffffffU

#endif /* __FRER_TIMEOUT_MACRO__ */


/* macros for frer_timeout */
#define EMAC_REGS__INST_FRER_TIMEOUT__NUM                                                1

/* macros for BlueprintGlobalNameSpace::frer_red_tag */
#ifndef __EMAC_REGS__FRER_RED_TAG_MACRO__
#define __EMAC_REGS__FRER_RED_TAG_MACRO__

/* macros for field redundancy_tag */
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__SHIFT                                   0
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__WIDTH                                  16
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__MASK                          0x0000ffffU
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__RESET                              0xF1C1
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__READ(src) ((uint32_t)(src) & 0x0000ffffU)
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__FRER_RED_TAG__REDUNDANCY_TAG__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_29_16 */
#define EMAC_REGS__FRER_RED_TAG__RESERVED_29_16__SHIFT                                  16
#define EMAC_REGS__FRER_RED_TAG__RESERVED_29_16__WIDTH                                  14
#define EMAC_REGS__FRER_RED_TAG__RESERVED_29_16__MASK                          0x3fff0000U
#define EMAC_REGS__FRER_RED_TAG__RESERVED_29_16__RESET                                   0
#define EMAC_REGS__FRER_RED_TAG__RESERVED_29_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3fff0000U) >> 16)

/* macros for field six_byte_tag */
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__SHIFT                                    30
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__WIDTH                                     1
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__MASK                            0x40000000U
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__RESET                                     1
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__FRER_RED_TAG__SIX_BYTE_TAG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field strip_r_tag */
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__SHIFT                                     31
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__WIDTH                                      1
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__MASK                             0x80000000U
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__RESET                                      0
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__FRER_RED_TAG__STRIP_R_TAG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__FRER_RED_TAG__TYPE                                             uint32_t
#define EMAC_REGS__FRER_RED_TAG__READ                                          0xffffffffU
#define EMAC_REGS__FRER_RED_TAG__WRITE                                         0xffffffffU

#endif /* __FRER_RED_TAG_MACRO__ */


/* macros for frer_red_tag */
#define EMAC_REGS__INST_FRER_RED_TAG__NUM                                                1

/* macros for BlueprintGlobalNameSpace::frer_control_a */
#ifndef __EMAC_REGS__FRER_CONTROL_A_MACRO__
#define __EMAC_REGS__FRER_CONTROL_A_MACRO__

/* macros for field member_stream_1 */
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__SHIFT                                0
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__WIDTH                                4
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__MASK                       0x0000000fU
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__RESET                                0
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_1__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field member_stream_2 */
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__SHIFT                                4
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__WIDTH                                4
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__MASK                       0x000000f0U
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__RESET                                0
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__FRER_CONTROL_A__MEMBER_STREAM_2__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field offset_value */
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__SHIFT                                   8
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__WIDTH                                   9
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__MASK                          0x0001ff00U
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__RESET                                   0
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0001ff00U) >> 8)
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0001ff00U)
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0001ff00U)
#define EMAC_REGS__FRER_CONTROL_A__OFFSET_VALUE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0001ff00U)))

/* macros for field reserved_27_17 */
#define EMAC_REGS__FRER_CONTROL_A__RESERVED_27_17__SHIFT                                17
#define EMAC_REGS__FRER_CONTROL_A__RESERVED_27_17__WIDTH                                11
#define EMAC_REGS__FRER_CONTROL_A__RESERVED_27_17__MASK                        0x0ffe0000U
#define EMAC_REGS__FRER_CONTROL_A__RESERVED_27_17__RESET                                 0
#define EMAC_REGS__FRER_CONTROL_A__RESERVED_27_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0ffe0000U) >> 17)

/* macros for field use_r_tag */
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__SHIFT                                     28
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__WIDTH                                      1
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__MASK                             0x10000000U
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__RESET                                      0
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__FRER_CONTROL_A__USE_R_TAG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field en_seqrecrst_timer */
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__SHIFT                            29
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__WIDTH                             1
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__MASK                    0x20000000U
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__RESET                             0
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__FRER_CONTROL_A__EN_SEQRECRST_TIMER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field en_vector_rec_alg */
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__SHIFT                             30
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__WIDTH                              1
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__MASK                     0x40000000U
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__RESET                              0
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__FRER_CONTROL_A__EN_VECTOR_REC_ALG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field en_elimination */
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__SHIFT                                31
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__WIDTH                                 1
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__MASK                        0x80000000U
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__RESET                                 0
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__FRER_CONTROL_A__EN_ELIMINATION__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__FRER_CONTROL_A__TYPE                                           uint32_t
#define EMAC_REGS__FRER_CONTROL_A__READ                                        0xffffffffU
#define EMAC_REGS__FRER_CONTROL_A__WRITE                                       0xffffffffU

#endif /* __FRER_CONTROL_A_MACRO__ */


/* macros for frer_control_1_a */
#define EMAC_REGS__INST_FRER_CONTROL_1_A__NUM                                            1

/* macros for BlueprintGlobalNameSpace::frer_control_b */
#ifndef __EMAC_REGS__FRER_CONTROL_B_MACRO__
#define __EMAC_REGS__FRER_CONTROL_B_MACRO__

/* macros for field seq_rec_window */
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__SHIFT                                 0
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__WIDTH                                 6
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__MASK                        0x0000003fU
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__RESET                                 0
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000003fU)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000003fU)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000003fU) | ((uint32_t)(src) &\
                    0x0000003fU)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_REC_WINDOW__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000003fU)))

/* macros for field reserved_7_6 */
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_7_6__SHIFT                                   6
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_7_6__WIDTH                                   2
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_7_6__MASK                          0x000000c0U
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_7_6__RESET                                   0
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_7_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000c0U) >> 6)

/* macros for field seq_num_length */
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__SHIFT                                 8
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__WIDTH                                 5
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__MASK                        0x00001f00U
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__RESET                                 0
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001f00U) >> 8)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00001f00U)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001f00U) | (((uint32_t)(src) <<\
                    8) & 0x00001f00U)
#define EMAC_REGS__FRER_CONTROL_B__SEQ_NUM_LENGTH__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00001f00U)))

/* macros for field reserved_31_13 */
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_31_13__SHIFT                                13
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_31_13__WIDTH                                19
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_31_13__MASK                        0xffffe000U
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_31_13__RESET                                 0
#define EMAC_REGS__FRER_CONTROL_B__RESERVED_31_13__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffe000U) >> 13)
#define EMAC_REGS__FRER_CONTROL_B__TYPE                                           uint32_t
#define EMAC_REGS__FRER_CONTROL_B__READ                                        0xffffffffU
#define EMAC_REGS__FRER_CONTROL_B__WRITE                                       0xffffffffU

#endif /* __FRER_CONTROL_B_MACRO__ */


/* macros for frer_control_1_b */
#define EMAC_REGS__INST_FRER_CONTROL_1_B__NUM                                            1

/* macros for BlueprintGlobalNameSpace::frer_statistics_a */
#ifndef __EMAC_REGS__FRER_STATISTICS_A_MACRO__
#define __EMAC_REGS__FRER_STATISTICS_A_MACRO__

/* macros for field latent_errors */
#define EMAC_REGS__FRER_STATISTICS_A__LATENT_ERRORS__SHIFT                               0
#define EMAC_REGS__FRER_STATISTICS_A__LATENT_ERRORS__WIDTH                              10
#define EMAC_REGS__FRER_STATISTICS_A__LATENT_ERRORS__MASK                      0x000003ffU
#define EMAC_REGS__FRER_STATISTICS_A__LATENT_ERRORS__RESET                               0
#define EMAC_REGS__FRER_STATISTICS_A__LATENT_ERRORS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000003ffU)

/* macros for field reserved_15_10 */
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_15_10__SHIFT                             10
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_15_10__WIDTH                              6
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_15_10__MASK                     0x0000fc00U
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_15_10__RESET                              0
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_15_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fc00U) >> 10)

/* macros for field vec_rec_rogue */
#define EMAC_REGS__FRER_STATISTICS_A__VEC_REC_ROGUE__SHIFT                              16
#define EMAC_REGS__FRER_STATISTICS_A__VEC_REC_ROGUE__WIDTH                              10
#define EMAC_REGS__FRER_STATISTICS_A__VEC_REC_ROGUE__MASK                      0x03ff0000U
#define EMAC_REGS__FRER_STATISTICS_A__VEC_REC_ROGUE__RESET                               0
#define EMAC_REGS__FRER_STATISTICS_A__VEC_REC_ROGUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x03ff0000U) >> 16)

/* macros for field reserved_31_26 */
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_31_26__SHIFT                             26
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_31_26__WIDTH                              6
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_31_26__MASK                     0xfc000000U
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_31_26__RESET                              0
#define EMAC_REGS__FRER_STATISTICS_A__RESERVED_31_26__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfc000000U) >> 26)
#define EMAC_REGS__FRER_STATISTICS_A__TYPE                                        uint32_t
#define EMAC_REGS__FRER_STATISTICS_A__READ                                     0xffffffffU
#define EMAC_REGS__FRER_STATISTICS_A__RCLR                                     0x03ff03ffU

#endif /* __FRER_STATISTICS_A_MACRO__ */


/* macros for frer_statistics_1_a */
#define EMAC_REGS__INST_FRER_STATISTICS_1_A__NUM                                         1

/* macros for BlueprintGlobalNameSpace::frer_statistics_b */
#ifndef __EMAC_REGS__FRER_STATISTICS_B_MACRO__
#define __EMAC_REGS__FRER_STATISTICS_B_MACRO__

/* macros for field out_of_order */
#define EMAC_REGS__FRER_STATISTICS_B__OUT_OF_ORDER__SHIFT                                0
#define EMAC_REGS__FRER_STATISTICS_B__OUT_OF_ORDER__WIDTH                               10
#define EMAC_REGS__FRER_STATISTICS_B__OUT_OF_ORDER__MASK                       0x000003ffU
#define EMAC_REGS__FRER_STATISTICS_B__OUT_OF_ORDER__RESET                                0
#define EMAC_REGS__FRER_STATISTICS_B__OUT_OF_ORDER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000003ffU)

/* macros for field reserved_15_10 */
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_15_10__SHIFT                             10
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_15_10__WIDTH                              6
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_15_10__MASK                     0x0000fc00U
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_15_10__RESET                              0
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_15_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fc00U) >> 10)

/* macros for field seqrst_count */
#define EMAC_REGS__FRER_STATISTICS_B__SEQRST_COUNT__SHIFT                               16
#define EMAC_REGS__FRER_STATISTICS_B__SEQRST_COUNT__WIDTH                                8
#define EMAC_REGS__FRER_STATISTICS_B__SEQRST_COUNT__MASK                       0x00ff0000U
#define EMAC_REGS__FRER_STATISTICS_B__SEQRST_COUNT__RESET                                0
#define EMAC_REGS__FRER_STATISTICS_B__SEQRST_COUNT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field reserved_31_24 */
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_31_24__SHIFT                             24
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_31_24__WIDTH                              8
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_31_24__MASK                     0xff000000U
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_31_24__RESET                              0
#define EMAC_REGS__FRER_STATISTICS_B__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__FRER_STATISTICS_B__TYPE                                        uint32_t
#define EMAC_REGS__FRER_STATISTICS_B__READ                                     0xffffffffU
#define EMAC_REGS__FRER_STATISTICS_B__RCLR                                     0x00ff03ffU

#endif /* __FRER_STATISTICS_B_MACRO__ */


/* macros for frer_statistics_1_b */
#define EMAC_REGS__INST_FRER_STATISTICS_1_B__NUM                                         1

/* macros for frer_control_2_a */
#define EMAC_REGS__INST_FRER_CONTROL_2_A__NUM                                            1

/* macros for frer_control_2_b */
#define EMAC_REGS__INST_FRER_CONTROL_2_B__NUM                                            1

/* macros for frer_statistics_2_a */
#define EMAC_REGS__INST_FRER_STATISTICS_2_A__NUM                                         1

/* macros for frer_statistics_2_b */
#define EMAC_REGS__INST_FRER_STATISTICS_2_B__NUM                                         1

/* macros for frer_control_3_a */
#define EMAC_REGS__INST_FRER_CONTROL_3_A__NUM                                            1

/* macros for frer_control_3_b */
#define EMAC_REGS__INST_FRER_CONTROL_3_B__NUM                                            1

/* macros for frer_statistics_3_a */
#define EMAC_REGS__INST_FRER_STATISTICS_3_A__NUM                                         1

/* macros for frer_statistics_3_b */
#define EMAC_REGS__INST_FRER_STATISTICS_3_B__NUM                                         1

/* macros for frer_control_4_a */
#define EMAC_REGS__INST_FRER_CONTROL_4_A__NUM                                            1

/* macros for frer_control_4_b */
#define EMAC_REGS__INST_FRER_CONTROL_4_B__NUM                                            1

/* macros for frer_statistics_4_a */
#define EMAC_REGS__INST_FRER_STATISTICS_4_A__NUM                                         1

/* macros for frer_statistics_4_b */
#define EMAC_REGS__INST_FRER_STATISTICS_4_B__NUM                                         1

/* macros for frer_control_5_a */
#define EMAC_REGS__INST_FRER_CONTROL_5_A__NUM                                            1

/* macros for frer_control_5_b */
#define EMAC_REGS__INST_FRER_CONTROL_5_B__NUM                                            1

/* macros for frer_statistics_5_a */
#define EMAC_REGS__INST_FRER_STATISTICS_5_A__NUM                                         1

/* macros for frer_statistics_5_b */
#define EMAC_REGS__INST_FRER_STATISTICS_5_B__NUM                                         1

/* macros for frer_control_6_a */
#define EMAC_REGS__INST_FRER_CONTROL_6_A__NUM                                            1

/* macros for frer_control_6_b */
#define EMAC_REGS__INST_FRER_CONTROL_6_B__NUM                                            1

/* macros for frer_statistics_6_a */
#define EMAC_REGS__INST_FRER_STATISTICS_6_A__NUM                                         1

/* macros for frer_statistics_6_b */
#define EMAC_REGS__INST_FRER_STATISTICS_6_B__NUM                                         1

/* macros for frer_control_7_a */
#define EMAC_REGS__INST_FRER_CONTROL_7_A__NUM                                            1

/* macros for frer_control_7_b */
#define EMAC_REGS__INST_FRER_CONTROL_7_B__NUM                                            1

/* macros for frer_statistics_7_a */
#define EMAC_REGS__INST_FRER_STATISTICS_7_A__NUM                                         1

/* macros for frer_statistics_7_b */
#define EMAC_REGS__INST_FRER_STATISTICS_7_B__NUM                                         1

/* macros for frer_control_8_a */
#define EMAC_REGS__INST_FRER_CONTROL_8_A__NUM                                            1

/* macros for frer_control_8_b */
#define EMAC_REGS__INST_FRER_CONTROL_8_B__NUM                                            1

/* macros for frer_statistics_8_a */
#define EMAC_REGS__INST_FRER_STATISTICS_8_A__NUM                                         1

/* macros for frer_statistics_8_b */
#define EMAC_REGS__INST_FRER_STATISTICS_8_B__NUM                                         1

/* macros for frer_control_9_a */
#define EMAC_REGS__INST_FRER_CONTROL_9_A__NUM                                            1

/* macros for frer_control_9_b */
#define EMAC_REGS__INST_FRER_CONTROL_9_B__NUM                                            1

/* macros for frer_statistics_9_a */
#define EMAC_REGS__INST_FRER_STATISTICS_9_A__NUM                                         1

/* macros for frer_statistics_9_b */
#define EMAC_REGS__INST_FRER_STATISTICS_9_B__NUM                                         1

/* macros for frer_control_10_a */
#define EMAC_REGS__INST_FRER_CONTROL_10_A__NUM                                           1

/* macros for frer_control_10_b */
#define EMAC_REGS__INST_FRER_CONTROL_10_B__NUM                                           1

/* macros for frer_statistics_10_a */
#define EMAC_REGS__INST_FRER_STATISTICS_10_A__NUM                                        1

/* macros for frer_statistics_10_b */
#define EMAC_REGS__INST_FRER_STATISTICS_10_B__NUM                                        1

/* macros for frer_control_11_a */
#define EMAC_REGS__INST_FRER_CONTROL_11_A__NUM                                           1

/* macros for frer_control_11_b */
#define EMAC_REGS__INST_FRER_CONTROL_11_B__NUM                                           1

/* macros for frer_statistics_11_a */
#define EMAC_REGS__INST_FRER_STATISTICS_11_A__NUM                                        1

/* macros for frer_statistics_11_b */
#define EMAC_REGS__INST_FRER_STATISTICS_11_B__NUM                                        1

/* macros for frer_control_12_a */
#define EMAC_REGS__INST_FRER_CONTROL_12_A__NUM                                           1

/* macros for frer_control_12_b */
#define EMAC_REGS__INST_FRER_CONTROL_12_B__NUM                                           1

/* macros for frer_statistics_12_a */
#define EMAC_REGS__INST_FRER_STATISTICS_12_A__NUM                                        1

/* macros for frer_statistics_12_b */
#define EMAC_REGS__INST_FRER_STATISTICS_12_B__NUM                                        1

/* macros for frer_control_13_a */
#define EMAC_REGS__INST_FRER_CONTROL_13_A__NUM                                           1

/* macros for frer_control_13_b */
#define EMAC_REGS__INST_FRER_CONTROL_13_B__NUM                                           1

/* macros for frer_statistics_13_a */
#define EMAC_REGS__INST_FRER_STATISTICS_13_A__NUM                                        1

/* macros for frer_statistics_13_b */
#define EMAC_REGS__INST_FRER_STATISTICS_13_B__NUM                                        1

/* macros for frer_control_14_a */
#define EMAC_REGS__INST_FRER_CONTROL_14_A__NUM                                           1

/* macros for frer_control_14_b */
#define EMAC_REGS__INST_FRER_CONTROL_14_B__NUM                                           1

/* macros for frer_statistics_14_a */
#define EMAC_REGS__INST_FRER_STATISTICS_14_A__NUM                                        1

/* macros for frer_statistics_14_b */
#define EMAC_REGS__INST_FRER_STATISTICS_14_B__NUM                                        1

/* macros for frer_control_15_a */
#define EMAC_REGS__INST_FRER_CONTROL_15_A__NUM                                           1

/* macros for frer_control_15_b */
#define EMAC_REGS__INST_FRER_CONTROL_15_B__NUM                                           1

/* macros for frer_statistics_15_a */
#define EMAC_REGS__INST_FRER_STATISTICS_15_A__NUM                                        1

/* macros for frer_statistics_15_b */
#define EMAC_REGS__INST_FRER_STATISTICS_15_B__NUM                                        1

/* macros for frer_control_16_a */
#define EMAC_REGS__INST_FRER_CONTROL_16_A__NUM                                           1

/* macros for frer_control_16_b */
#define EMAC_REGS__INST_FRER_CONTROL_16_B__NUM                                           1

/* macros for frer_statistics_16_a */
#define EMAC_REGS__INST_FRER_STATISTICS_16_A__NUM                                        1

/* macros for frer_statistics_16_b */
#define EMAC_REGS__INST_FRER_STATISTICS_16_B__NUM                                        1

/* macros for BlueprintGlobalNameSpace::tx_descr_rd_buf_ctl_q03 */
#ifndef __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03_MACRO__
#define __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03_MACRO__

/* macros for field q_0_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_0_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_1_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_1_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_2_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__SHIFT                   16
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__MASK           0x000f0000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_2_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__SHIFT                    20
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__MASK            0x00f00000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_3_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__SHIFT                   24
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__MASK           0x0f000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_3_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__SHIFT                    28
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__MASK            0xf0000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__TYPE                                  uint32_t
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__READ                               0xffffffffU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q03__WRITE                              0xffffffffU

#endif /* __TX_DESCR_RD_BUF_CTL_Q03_MACRO__ */


/* macros for tx_descr_rd_buf_ctl_q03 */
#define EMAC_REGS__INST_TX_DESCR_RD_BUF_CTL_Q03__NUM                                     1

/* macros for BlueprintGlobalNameSpace::tx_descr_rd_buf_ctl_q47 */
#ifndef __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47_MACRO__
#define __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47_MACRO__

/* macros for field q_4_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_4_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_5_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_5_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_6_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__SHIFT                   16
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__MASK           0x000f0000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_6_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__SHIFT                    20
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__MASK            0x00f00000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_7_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__SHIFT                   24
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__MASK           0x0f000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_7_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__SHIFT                    28
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__MASK            0xf0000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__TYPE                                  uint32_t
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__READ                               0xffffffffU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q47__WRITE                              0xffffffffU

#endif /* __TX_DESCR_RD_BUF_CTL_Q47_MACRO__ */


/* macros for tx_descr_rd_buf_ctl_q47 */
#define EMAC_REGS__INST_TX_DESCR_RD_BUF_CTL_Q47__NUM                                     1

/* macros for BlueprintGlobalNameSpace::tx_descr_rd_buf_ctl_q8b */
#ifndef __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B_MACRO__
#define __EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B_MACRO__

/* macros for field q_8_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_8_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_9_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_9_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_10_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__SHIFT                  16
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__MASK          0x000f0000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_10_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__SHIFT                   20
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__MASK           0x00f00000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_11_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__SHIFT                  24
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__MASK          0x0f000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_11_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__SHIFT                   28
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__MASK           0xf0000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__TYPE                                  uint32_t
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__READ                               0xffffffffU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_Q8B__WRITE                              0xffffffffU

#endif /* __TX_DESCR_RD_BUF_CTL_Q8B_MACRO__ */


/* macros for tx_descr_rd_buf_ctl_q8b */
#define EMAC_REGS__INST_TX_DESCR_RD_BUF_CTL_Q8B__NUM                                     1

/* macros for BlueprintGlobalNameSpace::tx_descr_rd_buf_ctl_qcf */
#ifndef __EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF_MACRO__
#define __EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF_MACRO__

/* macros for field q_12_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__SHIFT                   0
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__MASK          0x0000000fU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_12_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__SHIFT                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__MASK           0x000000f0U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_13_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__SHIFT                   8
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__MASK          0x00000f00U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_13_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__SHIFT                   12
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__MASK           0x0000f000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_14_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__SHIFT                  16
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__MASK          0x000f0000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_14_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__SHIFT                   20
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__MASK           0x00f00000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_15_high_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__SHIFT                  24
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__MASK          0x0f000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_15_low_watermark */
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__SHIFT                   28
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__MASK           0xf0000000U
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__TYPE                                  uint32_t
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__READ                               0xffffffffU
#define EMAC_REGS__TX_DESCR_RD_BUF_CTL_QCF__WRITE                              0xffffffffU

#endif /* __TX_DESCR_RD_BUF_CTL_QCF_MACRO__ */


/* macros for tx_descr_rd_buf_ctl_qcf */
#define EMAC_REGS__INST_TX_DESCR_RD_BUF_CTL_QCF__NUM                                     1

/* macros for BlueprintGlobalNameSpace::rx_descr_rd_buf_ctl_q03 */
#ifndef __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03_MACRO__
#define __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03_MACRO__

/* macros for field q_0_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_0_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_0_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_1_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_1_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_1_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_2_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__SHIFT                   16
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__MASK           0x000f0000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_2_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__SHIFT                    20
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__MASK            0x00f00000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_2_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_3_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__SHIFT                   24
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__MASK           0x0f000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_3_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__SHIFT                    28
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__MASK            0xf0000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__Q_3_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__TYPE                                  uint32_t
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__READ                               0xffffffffU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q03__WRITE                              0xffffffffU

#endif /* __RX_DESCR_RD_BUF_CTL_Q03_MACRO__ */


/* macros for rx_descr_rd_buf_ctl_q03 */
#define EMAC_REGS__INST_RX_DESCR_RD_BUF_CTL_Q03__NUM                                     1

/* macros for BlueprintGlobalNameSpace::rx_descr_rd_buf_ctl_q47 */
#ifndef __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47_MACRO__
#define __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47_MACRO__

/* macros for field q_4_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_4_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_4_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_5_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_5_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_5_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_6_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__SHIFT                   16
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__MASK           0x000f0000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_6_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__SHIFT                    20
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__MASK            0x00f00000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_6_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_7_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__SHIFT                   24
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__MASK           0x0f000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_7_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__SHIFT                    28
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__MASK            0xf0000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__Q_7_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__TYPE                                  uint32_t
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__READ                               0xffffffffU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q47__WRITE                              0xffffffffU

#endif /* __RX_DESCR_RD_BUF_CTL_Q47_MACRO__ */


/* macros for rx_descr_rd_buf_ctl_q47 */
#define EMAC_REGS__INST_RX_DESCR_RD_BUF_CTL_Q47__NUM                                     1

/* macros for BlueprintGlobalNameSpace::rx_descr_rd_buf_ctl_q8b */
#ifndef __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B_MACRO__
#define __EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B_MACRO__

/* macros for field q_8_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__SHIFT                    0
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__MASK           0x0000000fU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_8_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__SHIFT                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__MASK            0x000000f0U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_8_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_9_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__SHIFT                    8
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__MASK           0x00000f00U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_9_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__SHIFT                    12
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__WIDTH                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__MASK            0x0000f000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__RESET                     4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_9_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_10_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__SHIFT                  16
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__MASK          0x000f0000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_10_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__SHIFT                   20
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__MASK           0x00f00000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_10_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_11_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__SHIFT                  24
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__MASK          0x0f000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_11_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__SHIFT                   28
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__MASK           0xf0000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__Q_11_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__TYPE                                  uint32_t
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__READ                               0xffffffffU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_Q8B__WRITE                              0xffffffffU

#endif /* __RX_DESCR_RD_BUF_CTL_Q8B_MACRO__ */


/* macros for rx_descr_rd_buf_ctl_q8b */
#define EMAC_REGS__INST_RX_DESCR_RD_BUF_CTL_Q8B__NUM                                     1

/* macros for BlueprintGlobalNameSpace::rx_descr_rd_buf_ctl_qcf */
#ifndef __EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF_MACRO__
#define __EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF_MACRO__

/* macros for field q_12_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__SHIFT                   0
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__MASK          0x0000000fU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field q_12_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__SHIFT                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__MASK           0x000000f0U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_12_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field q_13_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__SHIFT                   8
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__MASK          0x00000f00U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000f00U) >> 8)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000f00U) | (((uint32_t)(src) <<\
                    8) & 0x00000f00U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000f00U)))

/* macros for field q_13_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__SHIFT                   12
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__MASK           0x0000f000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000f000U) >> 12)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000f000U) | (((uint32_t)(src) <<\
                    12) & 0x0000f000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_13_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x0000f000U)))

/* macros for field q_14_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__SHIFT                  16
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__MASK          0x000f0000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000f0000U) | (((uint32_t)(src) <<\
                    16) & 0x000f0000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x000f0000U)))

/* macros for field q_14_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__SHIFT                   20
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__MASK           0x00f00000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00f00000U) >> 20)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00f00000U) | (((uint32_t)(src) <<\
                    20) & 0x00f00000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_14_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00f00000U)))

/* macros for field q_15_high_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__SHIFT                  24
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__WIDTH                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__MASK          0x0f000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__RESET                   4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f000000U) >> 24)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f000000U) | (((uint32_t)(src) <<\
                    24) & 0x0f000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_HIGH_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x0f000000U)))

/* macros for field q_15_low_watermark */
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__SHIFT                   28
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__WIDTH                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__MASK           0xf0000000U
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__RESET                    4
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xf0000000U) | (((uint32_t)(src) <<\
                    28) & 0xf0000000U)
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__Q_15_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0xf0000000U)))
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__TYPE                                  uint32_t
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__READ                               0xffffffffU
#define EMAC_REGS__RX_DESCR_RD_BUF_CTL_QCF__WRITE                              0xffffffffU

#endif /* __RX_DESCR_RD_BUF_CTL_QCF_MACRO__ */


/* macros for rx_descr_rd_buf_ctl_qcf */
#define EMAC_REGS__INST_RX_DESCR_RD_BUF_CTL_QCF__NUM                                     1

/* macros for BlueprintGlobalNameSpace::gem_axi_xacts_rd_qx */
#ifndef __EMAC_REGS__GEM_AXI_XACTS_RD_QX_MACRO__
#define __EMAC_REGS__GEM_AXI_XACTS_RD_QX_MACRO__

/* macros for field max_rx_descr_rd */
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__SHIFT                           0
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__WIDTH                           8
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__MASK                  0x000000ffU
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__RESET                        0xff
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_RX_DESCR_RD__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field max_tx_descr_rd */
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__SHIFT                           8
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__WIDTH                           8
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__MASK                  0x0000ff00U
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__RESET                        0xff
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DESCR_RD__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field max_tx_data_rd */
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__SHIFT                           16
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__WIDTH                            8
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__MASK                   0x00ff0000U
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__RESET                         0xff
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__MAX_TX_DATA_RD__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field reserved_31_24 */
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__RESERVED_31_24__SHIFT                           24
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__RESERVED_31_24__WIDTH                            8
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__RESERVED_31_24__MASK                   0xff000000U
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__RESERVED_31_24__RESET                            0
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__TYPE                                      uint32_t
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__READ                                   0xffffffffU
#define EMAC_REGS__GEM_AXI_XACTS_RD_QX__WRITE                                  0xffffffffU

#endif /* __GEM_AXI_XACTS_RD_QX_MACRO__ */


/* macros for gem_axi_xacts_rd_q0 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q0__NUM                                         1

/* macros for BlueprintGlobalNameSpace::gem_axi_xacts_wr_qx */
#ifndef __EMAC_REGS__GEM_AXI_XACTS_WR_QX_MACRO__
#define __EMAC_REGS__GEM_AXI_XACTS_WR_QX_MACRO__

/* macros for field max_rx_descr_wr */
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__SHIFT                           0
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__WIDTH                           8
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__MASK                  0x000000ffU
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__RESET                        0xff
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DESCR_WR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field max_tx_descr_wr */
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__SHIFT                           8
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__WIDTH                           8
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__MASK                  0x0000ff00U
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__RESET                        0xff
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_TX_DESCR_WR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field max_rx_data_wr */
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__SHIFT                           16
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__WIDTH                            8
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__MASK                   0x00ff0000U
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__RESET                         0xff
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00ff0000U)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00ff0000U) | (((uint32_t)(src) <<\
                    16) & 0x00ff0000U)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__MAX_RX_DATA_WR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00ff0000U)))

/* macros for field reserved_31_24 */
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__RESERVED_31_24__SHIFT                           24
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__RESERVED_31_24__WIDTH                            8
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__RESERVED_31_24__MASK                   0xff000000U
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__RESERVED_31_24__RESET                            0
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__TYPE                                      uint32_t
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__READ                                   0xffffffffU
#define EMAC_REGS__GEM_AXI_XACTS_WR_QX__WRITE                                  0xffffffffU

#endif /* __GEM_AXI_XACTS_WR_QX_MACRO__ */


/* macros for gem_axi_xacts_wr_q0 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q0__NUM                                         1

/* macros for gem_axi_xacts_rd_q1 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q1__NUM                                         1

/* macros for gem_axi_xacts_wr_q1 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q1__NUM                                         1

/* macros for gem_axi_xacts_rd_q2 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q2__NUM                                         1

/* macros for gem_axi_xacts_wr_q2 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q2__NUM                                         1

/* macros for gem_axi_xacts_rd_q3 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q3__NUM                                         1

/* macros for gem_axi_xacts_wr_q3 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q3__NUM                                         1

/* macros for gem_axi_xacts_rd_q4 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q4__NUM                                         1

/* macros for gem_axi_xacts_wr_q4 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q4__NUM                                         1

/* macros for gem_axi_xacts_rd_q5 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q5__NUM                                         1

/* macros for gem_axi_xacts_wr_q5 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q5__NUM                                         1

/* macros for gem_axi_xacts_rd_q6 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q6__NUM                                         1

/* macros for gem_axi_xacts_wr_q6 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q6__NUM                                         1

/* macros for gem_axi_xacts_rd_q7 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q7__NUM                                         1

/* macros for gem_axi_xacts_wr_q7 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q7__NUM                                         1

/* macros for gem_axi_xacts_rd_q8 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q8__NUM                                         1

/* macros for gem_axi_xacts_wr_q8 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q8__NUM                                         1

/* macros for gem_axi_xacts_rd_q9 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q9__NUM                                         1

/* macros for gem_axi_xacts_wr_q9 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q9__NUM                                         1

/* macros for gem_axi_xacts_rd_q10 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q10__NUM                                        1

/* macros for gem_axi_xacts_wr_q10 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q10__NUM                                        1

/* macros for gem_axi_xacts_rd_q11 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q11__NUM                                        1

/* macros for gem_axi_xacts_wr_q11 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q11__NUM                                        1

/* macros for gem_axi_xacts_rd_q12 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q12__NUM                                        1

/* macros for gem_axi_xacts_wr_q12 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q12__NUM                                        1

/* macros for gem_axi_xacts_rd_q13 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q13__NUM                                        1

/* macros for gem_axi_xacts_wr_q13 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q13__NUM                                        1

/* macros for gem_axi_xacts_rd_q14 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q14__NUM                                        1

/* macros for gem_axi_xacts_wr_q14 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q14__NUM                                        1

/* macros for gem_axi_xacts_rd_q15 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_RD_Q15__NUM                                        1

/* macros for gem_axi_xacts_wr_q15 */
#define EMAC_REGS__INST_GEM_AXI_XACTS_WR_Q15__NUM                                        1

/* macros for BlueprintGlobalNameSpace::usx_control_register */
#ifndef __EMAC_REGS__USX_CONTROL_REGISTER_MACRO__
#define __EMAC_REGS__USX_CONTROL_REGISTER_MACRO__

/* macros for field signal_ok */
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__SHIFT                                0
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__WIDTH                                1
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__MASK                       0x00000001U
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__RESET                                0
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_CONTROL_REGISTER__SIGNAL_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field tx_datapath_en */
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__SHIFT                           1
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__WIDTH                           1
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__MASK                  0x00000002U
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__RESET                           0
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_DATAPATH_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_sync_reset */
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__SHIFT                            2
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__WIDTH                            1
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__MASK                   0x00000004U
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__RESET                            0
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SYNC_RESET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field reserved_3 */
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__SHIFT                               3
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__WIDTH                               1
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__MASK                      0x00000008U
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__RESET                               0
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field fec_enable */
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__SHIFT                               4
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__WIDTH                               1
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__MASK                      0x00000010U
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__RESET                               0
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field fec_ena_err_ind */
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__SHIFT                          5
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__WIDTH                          1
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__MASK                 0x00000020U
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__RESET                          0
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__USX_CONTROL_REGISTER__FEC_ENA_ERR_IND__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_7_6 */
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_7_6__SHIFT                             6
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_7_6__WIDTH                             2
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_7_6__MASK                    0x000000c0U
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_7_6__RESET                             0
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_7_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000c0U) >> 6)

/* macros for field tx_scr_bypass */
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__SHIFT                            8
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__WIDTH                            1
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__MASK                   0x00000100U
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__RESET                            0
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__USX_CONTROL_REGISTER__TX_SCR_BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field rx_scr_bypass */
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__SHIFT                            9
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__WIDTH                            1
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__MASK                   0x00000200U
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__RESET                            0
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__USX_CONTROL_REGISTER__RX_SCR_BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field reserved_11_10 */
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_11_10__SHIFT                          10
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_11_10__WIDTH                           2
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_11_10__MASK                  0x00000c00U
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_11_10__RESET                           0
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_11_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000c00U) >> 10)

/* macros for field serdes_rate */
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__SHIFT                             12
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__WIDTH                              2
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__MASK                     0x00003000U
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__RESET                              1
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00003000U) >> 12)
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00003000U)
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00003000U) | (((uint32_t)(src) <<\
                    12) & 0x00003000U)
#define EMAC_REGS__USX_CONTROL_REGISTER__SERDES_RATE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00003000U)))

/* macros for field hs_mac_speed */
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__SHIFT                            14
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__WIDTH                             3
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__MASK                    0x0001c000U
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__RESET                             0
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0001c000U) >> 14)
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x0001c000U)
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001c000U) | (((uint32_t)(src) <<\
                    14) & 0x0001c000U)
#define EMAC_REGS__USX_CONTROL_REGISTER__HS_MAC_SPEED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x0001c000U)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_31_17__SHIFT                          17
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_31_17__WIDTH                          15
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_31_17__MASK                  0xfffe0000U
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_31_17__RESET                           0
#define EMAC_REGS__USX_CONTROL_REGISTER__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__USX_CONTROL_REGISTER__TYPE                                     uint32_t
#define EMAC_REGS__USX_CONTROL_REGISTER__READ                                  0xffffffffU
#define EMAC_REGS__USX_CONTROL_REGISTER__WRITE                                 0xffffffffU

#endif /* __USX_CONTROL_REGISTER_MACRO__ */


/* macros for usx_control_register */
#define EMAC_REGS__INST_USX_CONTROL_REGISTER__NUM                                        1

/* macros for BlueprintGlobalNameSpace::usx_test_control */
#ifndef __EMAC_REGS__USX_TEST_CONTROL_MACRO__
#define __EMAC_REGS__USX_TEST_CONTROL_MACRO__

/* macros for field mii_lpbk_en */
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__SHIFT                                  0
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__WIDTH                                  1
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__MASK                         0x00000001U
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__RESET                                  0
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_TEST_CONTROL__MII_LPBK_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field scr_lpbk_en */
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__SHIFT                                  1
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__WIDTH                                  1
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__MASK                         0x00000002U
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__RESET                                  0
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__USX_TEST_CONTROL__SCR_LPBK_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_3_2 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_3_2__SHIFT                                 2
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_3_2__WIDTH                                 2
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_3_2__MASK                        0x0000000cU
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_3_2__RESET                                 0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_3_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000000cU) >> 2)

/* macros for field tx_tst_en */
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__SHIFT                                    4
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__WIDTH                                    1
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__MASK                           0x00000010U
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__RESET                                    0
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field tx_scr_idle_en */
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__SHIFT                               5
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__WIDTH                               1
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__MASK                      0x00000020U
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SCR_IDLE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field tx_tst_dat_sel */
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__SHIFT                               6
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__WIDTH                               1
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__MASK                      0x00000040U
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__USX_TEST_CONTROL__TX_TST_DAT_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_7 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__SHIFT                                   7
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__WIDTH                                   1
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__MASK                          0x00000080U
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__RESET                                   0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field tx_prbs9_en */
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__SHIFT                                  8
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__WIDTH                                  1
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__MASK                         0x00000100U
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__RESET                                  0
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS9_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field tx_prbs31_en */
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__SHIFT                                 9
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__WIDTH                                 1
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__MASK                        0x00000200U
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__RESET                                 0
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__USX_TEST_CONTROL__TX_PRBS31_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field reserved_11_10 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_11_10__SHIFT                              10
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_11_10__WIDTH                               2
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_11_10__MASK                      0x00000c00U
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_11_10__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_11_10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000c00U) >> 10)

/* macros for field tx_sqw_en */
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__SHIFT                                   12
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__WIDTH                                    1
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__MASK                           0x00001000U
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__RESET                                    0
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__USX_TEST_CONTROL__TX_SQW_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field reserved_15_13 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_15_13__SHIFT                              13
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_15_13__WIDTH                               3
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_15_13__MASK                      0x0000e000U
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_15_13__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_15_13__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000e000U) >> 13)

/* macros for field rx_tst_en */
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__SHIFT                                   16
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__WIDTH                                    1
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__MASK                           0x00010000U
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__RESET                                    0
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field rx_scr_idle_en */
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__SHIFT                              17
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__WIDTH                               1
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__MASK                      0x00020000U
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__USX_TEST_CONTROL__RX_SCR_IDLE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field rx_tst_dat_sel */
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__SHIFT                              18
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__WIDTH                               1
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__MASK                      0x00040000U
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__USX_TEST_CONTROL__RX_TST_DAT_SEL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field reserved_19 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__SHIFT                                 19
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__WIDTH                                  1
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__MASK                         0x00080000U
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__RESET                                  0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_19__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field rx_prbs9_en */
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__SHIFT                                 20
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__WIDTH                                  1
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__MASK                         0x00100000U
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__RESET                                  0
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS9_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field rx_prbs31_en */
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__SHIFT                                21
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__WIDTH                                 1
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__MASK                        0x00200000U
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__RESET                                 0
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__USX_TEST_CONTROL__RX_PRBS31_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field reserved_31_22 */
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_31_22__SHIFT                              22
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_31_22__WIDTH                              10
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_31_22__MASK                      0xffc00000U
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_31_22__RESET                               0
#define EMAC_REGS__USX_TEST_CONTROL__RESERVED_31_22__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffc00000U) >> 22)
#define EMAC_REGS__USX_TEST_CONTROL__TYPE                                         uint32_t
#define EMAC_REGS__USX_TEST_CONTROL__READ                                      0xffffffffU
#define EMAC_REGS__USX_TEST_CONTROL__WRITE                                     0xffffffffU

#endif /* __USX_TEST_CONTROL_MACRO__ */


/* macros for usx_test_control */
#define EMAC_REGS__INST_USX_TEST_CONTROL__NUM                                            1

/* macros for BlueprintGlobalNameSpace::usx_status_register */
#ifndef __EMAC_REGS__USX_STATUS_REGISTER_MACRO__
#define __EMAC_REGS__USX_STATUS_REGISTER_MACRO__

/* macros for field block_lock */
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__SHIFT                                0
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__WIDTH                                1
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__MASK                       0x00000001U
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__RESET                                0
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_STATUS_REGISTER__BLOCK_LOCK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_26_1 */
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_26_1__SHIFT                             1
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_26_1__WIDTH                            26
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_26_1__MASK                    0x07fffffeU
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_26_1__RESET                             0
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_26_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x07fffffeU) >> 1)

/* macros for field rx_fault */
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__SHIFT                                 27
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__WIDTH                                  1
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__MASK                         0x08000000U
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__RESET                                  0
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__USX_STATUS_REGISTER__RX_FAULT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field tx_fault */
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__SHIFT                                 28
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__WIDTH                                  1
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__MASK                         0x10000000U
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__RESET                                  0
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__USX_STATUS_REGISTER__TX_FAULT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field hi_bit_error */
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__SHIFT                             29
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__WIDTH                              1
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__MASK                     0x20000000U
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__RESET                              0
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__USX_STATUS_REGISTER__HI_BIT_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field reserved_30 */
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__SHIFT                              30
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__WIDTH                               1
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__MASK                      0x40000000U
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__RESET                               0
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__USX_STATUS_REGISTER__RESERVED_30__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field ctc_o_u_flow */
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__SHIFT                             31
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__WIDTH                              1
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__MASK                     0x80000000U
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__RESET                              0
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__USX_STATUS_REGISTER__CTC_O_U_FLOW__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__USX_STATUS_REGISTER__TYPE                                      uint32_t
#define EMAC_REGS__USX_STATUS_REGISTER__READ                                   0xffffffffU

#endif /* __USX_STATUS_REGISTER_MACRO__ */


/* macros for usx_status_register */
#define EMAC_REGS__INST_USX_STATUS_REGISTER__NUM                                         1

/* macros for BlueprintGlobalNameSpace::usx_test_seed_a_lower */
#ifndef __EMAC_REGS__USX_TEST_SEED_A_LOWER_MACRO__
#define __EMAC_REGS__USX_TEST_SEED_A_LOWER_MACRO__

/* macros for field seed_a_low */
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__SHIFT                              0
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__WIDTH                             32
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__MASK                     0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__RESET                              0
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__SEED_A_LOW__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__TYPE                                    uint32_t
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__READ                                 0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_A_LOWER__WRITE                                0xffffffffU

#endif /* __USX_TEST_SEED_A_LOWER_MACRO__ */


/* macros for usx_test_seed_a_lower */
#define EMAC_REGS__INST_USX_TEST_SEED_A_LOWER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_test_seed_a_upper */
#ifndef __EMAC_REGS__USX_TEST_SEED_A_UPPER_MACRO__
#define __EMAC_REGS__USX_TEST_SEED_A_UPPER_MACRO__

/* macros for field seed_a_upper */
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__SHIFT                            0
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__WIDTH                           26
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__MASK                   0x03ffffffU
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__RESET                            0
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ffffffU) | ((uint32_t)(src) &\
                    0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__SEED_A_UPPER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x03ffffffU)))

/* macros for field reserved_31_26 */
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__RESERVED_31_26__SHIFT                         26
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__RESERVED_31_26__WIDTH                          6
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__RESERVED_31_26__MASK                 0xfc000000U
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__RESERVED_31_26__RESET                          0
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__RESERVED_31_26__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfc000000U) >> 26)
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__TYPE                                    uint32_t
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__READ                                 0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_A_UPPER__WRITE                                0xffffffffU

#endif /* __USX_TEST_SEED_A_UPPER_MACRO__ */


/* macros for usx_test_seed_a_upper */
#define EMAC_REGS__INST_USX_TEST_SEED_A_UPPER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_test_seed_b_lower */
#ifndef __EMAC_REGS__USX_TEST_SEED_B_LOWER_MACRO__
#define __EMAC_REGS__USX_TEST_SEED_B_LOWER_MACRO__

/* macros for field seed_b_low */
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__SHIFT                              0
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__WIDTH                             32
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__MASK                     0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__RESET                              0
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__READ(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffffffffU) | ((uint32_t)(src) &\
                    0xffffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__SEED_B_LOW__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0xffffffffU)))
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__TYPE                                    uint32_t
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__READ                                 0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_B_LOWER__WRITE                                0xffffffffU

#endif /* __USX_TEST_SEED_B_LOWER_MACRO__ */


/* macros for usx_test_seed_b_lower */
#define EMAC_REGS__INST_USX_TEST_SEED_B_LOWER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_test_seed_b_upper */
#ifndef __EMAC_REGS__USX_TEST_SEED_B_UPPER_MACRO__
#define __EMAC_REGS__USX_TEST_SEED_B_UPPER_MACRO__

/* macros for field seed_b_upper */
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__SHIFT                            0
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__WIDTH                           26
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__MASK                   0x03ffffffU
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__RESET                            0
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__READ(src) \
                    ((uint32_t)(src)\
                    & 0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x03ffffffU) | ((uint32_t)(src) &\
                    0x03ffffffU)
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__SEED_B_UPPER__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x03ffffffU)))

/* macros for field reserved_31_26 */
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__RESERVED_31_26__SHIFT                         26
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__RESERVED_31_26__WIDTH                          6
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__RESERVED_31_26__MASK                 0xfc000000U
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__RESERVED_31_26__RESET                          0
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__RESERVED_31_26__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfc000000U) >> 26)
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__TYPE                                    uint32_t
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__READ                                 0xffffffffU
#define EMAC_REGS__USX_TEST_SEED_B_UPPER__WRITE                                0xffffffffU

#endif /* __USX_TEST_SEED_B_UPPER_MACRO__ */


/* macros for usx_test_seed_b_upper */
#define EMAC_REGS__INST_USX_TEST_SEED_B_UPPER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_rx_decoder_error_counter */
#ifndef __EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER_MACRO__
#define __EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER_MACRO__

/* macros for field block_error_count */
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__SHIFT                0
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__WIDTH                8
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__MASK       0x000000ffU
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__RESET                0
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__BLOCK_ERROR_COUNT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__RESERVED_31_8__SHIFT                    8
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__RESERVED_31_8__WIDTH                   24
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__RESERVED_31_8__MASK           0xffffff00U
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__RESERVED_31_8__RESET                    0
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__TYPE                             uint32_t
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__READ                          0xffffffffU
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__WRITE                         0xffffffffU
#define EMAC_REGS__USX_RX_DECODER_ERROR_COUNTER__WOCLR                         0x000000ffU

#endif /* __USX_RX_DECODER_ERROR_COUNTER_MACRO__ */


/* macros for usx_rx_decoder_error_counter */
#define EMAC_REGS__INST_USX_RX_DECODER_ERROR_COUNTER__NUM                                1

/* macros for BlueprintGlobalNameSpace::usx_bit_error_counter */
#ifndef __EMAC_REGS__USX_BIT_ERROR_COUNTER_MACRO__
#define __EMAC_REGS__USX_BIT_ERROR_COUNTER_MACRO__

/* macros for field bit_error_count */
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__SHIFT                         0
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__WIDTH                        22
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__MASK                0x003fffffU
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__RESET                         0
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x003fffffU)
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x003fffffU)
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x003fffffU) | ((uint32_t)(src) &\
                    0x003fffffU)
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__BIT_ERROR_COUNT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x003fffffU)))

/* macros for field reserved_31_22 */
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__RESERVED_31_22__SHIFT                         22
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__RESERVED_31_22__WIDTH                         10
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__RESERVED_31_22__MASK                 0xffc00000U
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__RESERVED_31_22__RESET                          0
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__RESERVED_31_22__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffc00000U) >> 22)
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__TYPE                                    uint32_t
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__READ                                 0xffffffffU
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__WRITE                                0xffffffffU
#define EMAC_REGS__USX_BIT_ERROR_COUNTER__WOCLR                                0x003fffffU

#endif /* __USX_BIT_ERROR_COUNTER_MACRO__ */


/* macros for usx_bit_error_counter */
#define EMAC_REGS__INST_USX_BIT_ERROR_COUNTER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_test_pattern_error_counter */
#ifndef __EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER_MACRO__
#define __EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER_MACRO__

/* macros for field test_error_count */
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__SHIFT               0
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__WIDTH              16
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__MASK      0x0000ffffU
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__RESET               0
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TEST_ERROR_COUNT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__RESERVED_31_16__SHIFT                16
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__RESERVED_31_16__WIDTH                16
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__RESERVED_31_16__MASK        0xffff0000U
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__RESERVED_31_16__RESET                 0
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__TYPE                           uint32_t
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__READ                        0xffffffffU
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__WRITE                       0xffffffffU
#define EMAC_REGS__USX_TEST_PATTERN_ERROR_COUNTER__WOCLR                       0x0000ffffU

#endif /* __USX_TEST_PATTERN_ERROR_COUNTER_MACRO__ */


/* macros for usx_test_pattern_error_counter */
#define EMAC_REGS__INST_USX_TEST_PATTERN_ERROR_COUNTER__NUM                              1

/* macros for BlueprintGlobalNameSpace::usx_prbs_error_counter */
#ifndef __EMAC_REGS__USX_PRBS_ERROR_COUNTER_MACRO__
#define __EMAC_REGS__USX_PRBS_ERROR_COUNTER_MACRO__

/* macros for field prbs_rx_error_count */
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__SHIFT                    0
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__WIDTH                   12
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__MASK           0x00000fffU
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__RESET                    0
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000fffU)
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000fffU)
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000fffU) | ((uint32_t)(src) &\
                    0x00000fffU)
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__PRBS_RX_ERROR_COUNT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000fffU)))

/* macros for field reserved_31_12 */
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__RESERVED_31_12__SHIFT                        12
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__RESERVED_31_12__WIDTH                        20
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__RESERVED_31_12__MASK                0xfffff000U
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__RESERVED_31_12__RESET                         0
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__RESERVED_31_12__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff000U) >> 12)
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__TYPE                                   uint32_t
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__READ                                0xffffffffU
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__WRITE                               0xffffffffU
#define EMAC_REGS__USX_PRBS_ERROR_COUNTER__WOCLR                               0x00000fffU

#endif /* __USX_PRBS_ERROR_COUNTER_MACRO__ */


/* macros for usx_prbs_error_counter */
#define EMAC_REGS__INST_USX_PRBS_ERROR_COUNTER__NUM                                      1

/* macros for BlueprintGlobalNameSpace::usx_fec_error_counter */
#ifndef __EMAC_REGS__USX_FEC_ERROR_COUNTER_MACRO__
#define __EMAC_REGS__USX_FEC_ERROR_COUNTER_MACRO__

/* macros for field fec_block_corrected_count */
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__SHIFT               0
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__WIDTH              16
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__MASK      0x0000ffffU
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__RESET               0
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_CORRECTED_COUNT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field fec_block_error_count */
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__SHIFT                  16
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__WIDTH                  16
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__MASK          0xffff0000U
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__RESET                   0
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__FEC_BLOCK_ERROR_COUNT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__TYPE                                    uint32_t
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__READ                                 0xffffffffU
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__WRITE                                0xffffffffU
#define EMAC_REGS__USX_FEC_ERROR_COUNTER__WOCLR                                0xffffffffU

#endif /* __USX_FEC_ERROR_COUNTER_MACRO__ */


/* macros for usx_fec_error_counter */
#define EMAC_REGS__INST_USX_FEC_ERROR_COUNTER__NUM                                       1

/* macros for BlueprintGlobalNameSpace::usx_interrupt_status_register */
#ifndef __EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER_MACRO__
#define __EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__SHIFT                      0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__WIDTH                      1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__MASK             0x00000001U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__RESET                      0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field buffer_error */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__SHIFT                    1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__WIDTH                    1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__MASK           0x00000002U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BUFFER_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field reserved_2 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__SHIFT                      2
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__WIDTH                      1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__MASK             0x00000004U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__RESET                      0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field hi_bit_error */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__SHIFT                    3
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__WIDTH                    1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__MASK           0x00000008U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__HI_BIT_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field reserved_7_4 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_7_4__SHIFT                    4
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_7_4__WIDTH                    4
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_7_4__MASK           0x000000f0U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_7_4__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_7_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field block_locked */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__SHIFT                    8
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__WIDTH                    1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__MASK           0x00000100U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__BLOCK_LOCKED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_15_9__SHIFT                   9
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_15_9__WIDTH                   7
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_15_9__MASK          0x0000fe00U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_15_9__RESET                   0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field fec_uncorrectable_error */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__SHIFT        16
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__WIDTH         1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__MASK \
                    0x00010000U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__RESET         0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_UNCORRECTABLE_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)

/* macros for field reserved_19_17 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_19_17__SHIFT                 17
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_19_17__WIDTH                  3
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_19_17__MASK         0x000e0000U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_19_17__RESET                  0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_19_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000e0000U) >> 17)

/* macros for field fec_correctable_error */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__SHIFT          20
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__WIDTH           1
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__MASK  0x00100000U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__RESET           0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__FEC_CORRECTABLE_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)

/* macros for field reserved_31_21 */
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_31_21__SHIFT                 21
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_31_21__WIDTH                 11
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_31_21__MASK         0xffe00000U
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_31_21__RESET                  0
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__RESERVED_31_21__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffe00000U) >> 21)
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__TYPE                            uint32_t
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__READ                         0xffffffffU
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__WRITE                        0xffffffffU
#define EMAC_REGS__USX_INTERRUPT_STATUS_REGISTER__WOCLR                        0x0011010aU

#endif /* __USX_INTERRUPT_STATUS_REGISTER_MACRO__ */


/* macros for usx_interrupt_status_register */
#define EMAC_REGS__INST_USX_INTERRUPT_STATUS_REGISTER__NUM                               1

/* macros for BlueprintGlobalNameSpace::usx_interrupt_enable_register */
#ifndef __EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER_MACRO__
#define __EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__SHIFT                      0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__WIDTH                      1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__MASK             0x00000001U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__RESET                      0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field buffer_error_en */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__SHIFT                 1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__MASK        0x00000002U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__RESET                 0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BUFFER_ERROR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_2 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__SHIFT                      2
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__WIDTH                      1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__MASK             0x00000004U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__RESET                      0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field hi_bit_error_en */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__SHIFT                 3
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__MASK        0x00000008U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__RESET                 0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__HI_BIT_ERROR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_7_4 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_7_4__SHIFT                    4
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_7_4__WIDTH                    4
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_7_4__MASK           0x000000f0U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_7_4__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_7_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field block_locked_en */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__SHIFT                 8
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__MASK        0x00000100U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__RESET                 0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__BLOCK_LOCKED_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_15_9__SHIFT                   9
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_15_9__WIDTH                   7
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_15_9__MASK          0x0000fe00U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_15_9__RESET                   0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field fec_uncorrectable_error_en */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__SHIFT     16
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__WIDTH      1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__MASK \
                    0x00010000U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__RESET      0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_19_17 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_19_17__SHIFT                 17
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_19_17__WIDTH                  3
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_19_17__MASK         0x000e0000U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_19_17__RESET                  0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_19_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000e0000U) >> 17)

/* macros for field fec_correctable_error_en */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__SHIFT       20
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__WIDTH        1
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__MASK \
                    0x00100000U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__RESET        0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__FEC_CORRECTABLE_ERROR_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field reserved_31_21 */
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_31_21__SHIFT                 21
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_31_21__WIDTH                 11
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_31_21__MASK         0xffe00000U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_31_21__RESET                  0
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__RESERVED_31_21__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffe00000U) >> 21)
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__TYPE                            uint32_t
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__READ                         0xffeefef5U
#define EMAC_REGS__USX_INTERRUPT_ENABLE_REGISTER__WRITE                        0xffeefef5U

#endif /* __USX_INTERRUPT_ENABLE_REGISTER_MACRO__ */


/* macros for usx_interrupt_enable_register */
#define EMAC_REGS__INST_USX_INTERRUPT_ENABLE_REGISTER__NUM                               1

/* macros for BlueprintGlobalNameSpace::usx_interrupt_disable_register */
#ifndef __EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER_MACRO__
#define __EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__SHIFT                     0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__WIDTH                     1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__MASK            0x00000001U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__RESET                     0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field buffer_error_dis */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__SHIFT               1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__WIDTH               1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__MASK      0x00000002U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__RESET               0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BUFFER_ERROR_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_2 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__SHIFT                     2
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__WIDTH                     1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__MASK            0x00000004U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__RESET                     0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field hi_bit_error_dis */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__SHIFT               3
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__WIDTH               1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__MASK      0x00000008U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__RESET               0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__HI_BIT_ERROR_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_7_4 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_7_4__SHIFT                   4
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_7_4__WIDTH                   4
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_7_4__MASK          0x000000f0U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_7_4__RESET                   0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_7_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field block_locked_dis */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__SHIFT               8
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__WIDTH               1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__MASK      0x00000100U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__RESET               0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__BLOCK_LOCKED_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_15_9__SHIFT                  9
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_15_9__WIDTH                  7
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_15_9__MASK         0x0000fe00U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_15_9__RESET                  0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field fec_uncorrectable_error_dis */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__SHIFT   16
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__WIDTH    1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__MASK \
                    0x00010000U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__RESET    0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_UNCORRECTABLE_ERROR_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_19_17 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_19_17__SHIFT                17
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_19_17__WIDTH                 3
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_19_17__MASK        0x000e0000U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_19_17__RESET                 0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_19_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000e0000U) >> 17)

/* macros for field fec_correctable_error_dis */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__SHIFT     20
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__WIDTH      1
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__MASK \
                    0x00100000U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__RESET      0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__FEC_CORRECTABLE_ERROR_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field reserved_31_21 */
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_31_21__SHIFT                21
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_31_21__WIDTH                11
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_31_21__MASK        0xffe00000U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_31_21__RESET                 0
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__RESERVED_31_21__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffe00000U) >> 21)
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__TYPE                           uint32_t
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__READ                        0xffeefef5U
#define EMAC_REGS__USX_INTERRUPT_DISABLE_REGISTER__WRITE                       0xffeefef5U

#endif /* __USX_INTERRUPT_DISABLE_REGISTER_MACRO__ */


/* macros for usx_interrupt_disable_register */
#define EMAC_REGS__INST_USX_INTERRUPT_DISABLE_REGISTER__NUM                              1

/* macros for BlueprintGlobalNameSpace::usx_interrupt_mask_register */
#ifndef __EMAC_REGS__USX_INTERRUPT_MASK_REGISTER_MACRO__
#define __EMAC_REGS__USX_INTERRUPT_MASK_REGISTER_MACRO__

/* macros for field reserved_0 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__SHIFT                        0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__WIDTH                        1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__MASK               0x00000001U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__RESET                        0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field buffer_error_mask */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__SHIFT                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__MASK        0x00000002U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__RESET                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BUFFER_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_2 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__SHIFT                        2
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__WIDTH                        1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__MASK               0x00000004U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__RESET                        0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_2__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field hi_bit_error_mask */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__SHIFT                 3
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__MASK        0x00000008U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__RESET                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__HI_BIT_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_7_4 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_7_4__SHIFT                      4
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_7_4__WIDTH                      4
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_7_4__MASK             0x000000f0U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_7_4__RESET                      0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_7_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)

/* macros for field block_locked_mask */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__SHIFT                 8
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__WIDTH                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__MASK        0x00000100U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__RESET                 1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__BLOCK_LOCKED_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_15_9__SHIFT                     9
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_15_9__WIDTH                     7
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_15_9__MASK            0x0000fe00U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_15_9__RESET                     0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field fec_uncorrectable_error_mask */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__SHIFT     16
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__WIDTH      1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__MASK \
                    0x00010000U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__RESET      1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_UNCORRECTABLE_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field reserved_19_17 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_19_17__SHIFT                   17
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_19_17__WIDTH                    3
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_19_17__MASK           0x000e0000U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_19_17__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_19_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000e0000U) >> 17)

/* macros for field fec_correctable_error_mask */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__SHIFT       20
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__WIDTH        1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__MASK \
                    0x00100000U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__RESET        1
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__FEC_CORRECTABLE_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field reserved_31_21 */
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_31_21__SHIFT                   21
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_31_21__WIDTH                   11
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_31_21__MASK           0xffe00000U
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_31_21__RESET                    0
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__RESERVED_31_21__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffe00000U) >> 21)
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__TYPE                              uint32_t
#define EMAC_REGS__USX_INTERRUPT_MASK_REGISTER__READ                           0xffffffffU

#endif /* __USX_INTERRUPT_MASK_REGISTER_MACRO__ */


/* macros for usx_interrupt_mask_register */
#define EMAC_REGS__INST_USX_INTERRUPT_MASK_REGISTER__NUM                                 1

/* macros for BlueprintGlobalNameSpace::rx_q_flush */
#ifndef __EMAC_REGS__RX_Q_FLUSH_MACRO__
#define __EMAC_REGS__RX_Q_FLUSH_MACRO__

/* macros for field drop_all_frames */
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__SHIFT                                    0
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__WIDTH                                    1
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__MASK                           0x00000001U
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__RESET                                    0
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__READ(src)  ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__WRITE(src) ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ALL_FRAMES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field drop_on_resource_err */
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__SHIFT                               1
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__WIDTH                               1
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__MASK                      0x00000002U
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__RESET                               0
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__RX_Q_FLUSH__DROP_ON_RESOURCE_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field limit_num_bytes */
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__SHIFT                                    2
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__WIDTH                                    1
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__MASK                           0x00000004U
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__RESET                                    0
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_NUM_BYTES__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field limit_frame_size */
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__SHIFT                                   3
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__WIDTH                                   1
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__MASK                          0x00000008U
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__RESET                                   0
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__RX_Q_FLUSH__LIMIT_FRAME_SIZE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field reserved_15_4 */
#define EMAC_REGS__RX_Q_FLUSH__RESERVED_15_4__SHIFT                                      4
#define EMAC_REGS__RX_Q_FLUSH__RESERVED_15_4__WIDTH                                     12
#define EMAC_REGS__RX_Q_FLUSH__RESERVED_15_4__MASK                             0x0000fff0U
#define EMAC_REGS__RX_Q_FLUSH__RESERVED_15_4__RESET                                      0
#define EMAC_REGS__RX_Q_FLUSH__RESERVED_15_4__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fff0U) >> 4)

/* macros for field max_val */
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__SHIFT                                           16
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__WIDTH                                           16
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__MASK                                   0xffff0000U
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__RESET                                            0
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__READ(src)  (((uint32_t)(src) & 0xffff0000U) >> 16)
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__WRITE(src) (((uint32_t)(src) << 16) & 0xffff0000U)
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__RX_Q_FLUSH__MAX_VAL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__RX_Q_FLUSH__TYPE                                               uint32_t
#define EMAC_REGS__RX_Q_FLUSH__READ                                            0xffffffffU
#define EMAC_REGS__RX_Q_FLUSH__WRITE                                           0xffffffffU

#endif /* __RX_Q_FLUSH_MACRO__ */


/* macros for rx_q0_flush */
#define EMAC_REGS__INST_RX_Q0_FLUSH__NUM                                                 1

/* macros for rx_q1_flush */
#define EMAC_REGS__INST_RX_Q1_FLUSH__NUM                                                 1

/* macros for rx_q2_flush */
#define EMAC_REGS__INST_RX_Q2_FLUSH__NUM                                                 1

/* macros for rx_q3_flush */
#define EMAC_REGS__INST_RX_Q3_FLUSH__NUM                                                 1

/* macros for rx_q4_flush */
#define EMAC_REGS__INST_RX_Q4_FLUSH__NUM                                                 1

/* macros for rx_q5_flush */
#define EMAC_REGS__INST_RX_Q5_FLUSH__NUM                                                 1

/* macros for rx_q6_flush */
#define EMAC_REGS__INST_RX_Q6_FLUSH__NUM                                                 1

/* macros for rx_q7_flush */
#define EMAC_REGS__INST_RX_Q7_FLUSH__NUM                                                 1

/* macros for rx_q8_flush */
#define EMAC_REGS__INST_RX_Q8_FLUSH__NUM                                                 1

/* macros for rx_q9_flush */
#define EMAC_REGS__INST_RX_Q9_FLUSH__NUM                                                 1

/* macros for rx_q10_flush */
#define EMAC_REGS__INST_RX_Q10_FLUSH__NUM                                                1

/* macros for rx_q11_flush */
#define EMAC_REGS__INST_RX_Q11_FLUSH__NUM                                                1

/* macros for rx_q12_flush */
#define EMAC_REGS__INST_RX_Q12_FLUSH__NUM                                                1

/* macros for rx_q13_flush */
#define EMAC_REGS__INST_RX_Q13_FLUSH__NUM                                                1

/* macros for rx_q14_flush */
#define EMAC_REGS__INST_RX_Q14_FLUSH__NUM                                                1

/* macros for rx_q15_flush */
#define EMAC_REGS__INST_RX_Q15_FLUSH__NUM                                                1

/* macros for BlueprintGlobalNameSpace::scr2_rate_limit */
#ifndef __EMAC_REGS__SCR2_RATE_LIMIT_MACRO__
#define __EMAC_REGS__SCR2_RATE_LIMIT_MACRO__

/* macros for field interval_time */
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__SHIFT                                 0
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__WIDTH                                16
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__MASK                        0x0000ffffU
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__RESET                                 0
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__SCR2_RATE_LIMIT__INTERVAL_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field max_rate_val */
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__SHIFT                                 16
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__WIDTH                                 16
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__MASK                         0xffff0000U
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__RESET                                  0
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0xffff0000U)
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xffff0000U) | (((uint32_t)(src) <<\
                    16) & 0xffff0000U)
#define EMAC_REGS__SCR2_RATE_LIMIT__MAX_RATE_VAL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0xffff0000U)))
#define EMAC_REGS__SCR2_RATE_LIMIT__TYPE                                          uint32_t
#define EMAC_REGS__SCR2_RATE_LIMIT__READ                                       0xffffffffU
#define EMAC_REGS__SCR2_RATE_LIMIT__WRITE                                      0xffffffffU

#endif /* __SCR2_RATE_LIMIT_MACRO__ */


/* macros for scr2_reg0_rate_limit */
#define EMAC_REGS__INST_SCR2_REG0_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg1_rate_limit */
#define EMAC_REGS__INST_SCR2_REG1_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg2_rate_limit */
#define EMAC_REGS__INST_SCR2_REG2_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg3_rate_limit */
#define EMAC_REGS__INST_SCR2_REG3_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg4_rate_limit */
#define EMAC_REGS__INST_SCR2_REG4_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg5_rate_limit */
#define EMAC_REGS__INST_SCR2_REG5_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg6_rate_limit */
#define EMAC_REGS__INST_SCR2_REG6_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg7_rate_limit */
#define EMAC_REGS__INST_SCR2_REG7_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg8_rate_limit */
#define EMAC_REGS__INST_SCR2_REG8_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg9_rate_limit */
#define EMAC_REGS__INST_SCR2_REG9_RATE_LIMIT__NUM                                        1

/* macros for scr2_reg10_rate_limit */
#define EMAC_REGS__INST_SCR2_REG10_RATE_LIMIT__NUM                                       1

/* macros for scr2_reg11_rate_limit */
#define EMAC_REGS__INST_SCR2_REG11_RATE_LIMIT__NUM                                       1

/* macros for scr2_reg12_rate_limit */
#define EMAC_REGS__INST_SCR2_REG12_RATE_LIMIT__NUM                                       1

/* macros for scr2_reg13_rate_limit */
#define EMAC_REGS__INST_SCR2_REG13_RATE_LIMIT__NUM                                       1

/* macros for scr2_reg14_rate_limit */
#define EMAC_REGS__INST_SCR2_REG14_RATE_LIMIT__NUM                                       1

/* macros for scr2_reg15_rate_limit */
#define EMAC_REGS__INST_SCR2_REG15_RATE_LIMIT__NUM                                       1

/* macros for BlueprintGlobalNameSpace::scr2_rate_status */
#ifndef __EMAC_REGS__SCR2_RATE_STATUS_MACRO__
#define __EMAC_REGS__SCR2_RATE_STATUS_MACRO__

/* macros for field scr2_0_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__SHIFT                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__MASK                  0x00000001U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_0_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field scr2_1_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__SHIFT                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__MASK                  0x00000002U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_1_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field scr2_2_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__SHIFT                           2
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__MASK                  0x00000004U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_2_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field scr2_3_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__SHIFT                           3
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__MASK                  0x00000008U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_3_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field scr2_4_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__SHIFT                           4
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__MASK                  0x00000010U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_4_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field scr2_5_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__SHIFT                           5
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__MASK                  0x00000020U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_5_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field scr2_6_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__SHIFT                           6
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__MASK                  0x00000040U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_6_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field scr2_7_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__SHIFT                           7
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__MASK                  0x00000080U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_7_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field scr2_8_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__SHIFT                           8
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__MASK                  0x00000100U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_8_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field scr2_9_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__SHIFT                           9
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__WIDTH                           1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__MASK                  0x00000200U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__RESET                           0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_9_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field scr2_10_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__SHIFT                         10
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__MASK                 0x00000400U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_10_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field scr2_11_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__SHIFT                         11
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__MASK                 0x00000800U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000800U) >> 11)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_11_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field scr2_12_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__SHIFT                         12
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__MASK                 0x00001000U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00001000U) >> 12)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_12_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field scr2_13_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__SHIFT                         13
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__MASK                 0x00002000U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00002000U) >> 13)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_13_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field scr2_14_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__SHIFT                         14
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__MASK                 0x00004000U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_14_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field scr2_15_excess_rate */
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__SHIFT                         15
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__WIDTH                          1
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__MASK                 0x00008000U
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__RESET                          0
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__SCR2_RATE_STATUS__SCR2_15_EXCESS_RATE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field reserved_31_16 */
#define EMAC_REGS__SCR2_RATE_STATUS__RESERVED_31_16__SHIFT                              16
#define EMAC_REGS__SCR2_RATE_STATUS__RESERVED_31_16__WIDTH                              16
#define EMAC_REGS__SCR2_RATE_STATUS__RESERVED_31_16__MASK                      0xffff0000U
#define EMAC_REGS__SCR2_RATE_STATUS__RESERVED_31_16__RESET                               0
#define EMAC_REGS__SCR2_RATE_STATUS__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__SCR2_RATE_STATUS__TYPE                                         uint32_t
#define EMAC_REGS__SCR2_RATE_STATUS__READ                                      0xffffffffU
#define EMAC_REGS__SCR2_RATE_STATUS__RCLR                                      0x0000ffffU

#endif /* __SCR2_RATE_STATUS_MACRO__ */


/* macros for scr2_rate_status */
#define EMAC_REGS__INST_SCR2_RATE_STATUS__NUM                                            1

/* macros for BlueprintGlobalNameSpace::q_control */
#ifndef __EMAC_REGS__Q_CONTROL_MACRO__
#define __EMAC_REGS__Q_CONTROL_MACRO__

/* macros for field max_tx_burst_len */
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__SHIFT                                    0
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__WIDTH                                    4
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__MASK                           0x0000000fU
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__RESET                                    2
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__READ(src)  ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__WRITE(src) ((uint32_t)(src) & 0x0000000fU)
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__Q_CONTROL__MAX_TX_BURST_LEN__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field max_rx_burst_len */
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__SHIFT                                    4
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__WIDTH                                    4
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__MASK                           0x000000f0U
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__RESET                                    2
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__Q_CONTROL__MAX_RX_BURST_LEN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field rx_buf_size */
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__SHIFT                                         8
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__WIDTH                                         8
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__MASK                                0x0000ff00U
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__RESET                                         2
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x0000ff00U)
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ff00U) | (((uint32_t)(src) <<\
                    8) & 0x0000ff00U)
#define EMAC_REGS__Q_CONTROL__RX_BUF_SIZE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x0000ff00U)))

/* macros for field hdr_data_splitting_en */
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__SHIFT                              16
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__WIDTH                               1
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__MASK                      0x00010000U
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__RESET                             0b0
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__Q_CONTROL__HDR_DATA_SPLITTING_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field rx_bd_extended_mode_en */
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__SHIFT                             17
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__WIDTH                              1
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__MASK                     0x00020000U
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__RESET                              0
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__Q_CONTROL__RX_BD_EXTENDED_MODE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field tx_bd_extended_mode_en */
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__SHIFT                             18
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__WIDTH                              1
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__MASK                     0x00040000U
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__RESET                              0
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__Q_CONTROL__TX_BD_EXTENDED_MODE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field transmit_start */
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__SHIFT                                     19
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__WIDTH                                      1
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__MASK                             0x00080000U
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__RESET                                      0
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_START__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field transmit_halt */
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__SHIFT                                      20
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__WIDTH                                       1
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__MASK                              0x00100000U
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__RESET                                       0
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__Q_CONTROL__TRANSMIT_HALT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field reserved_31 */
#define EMAC_REGS__Q_CONTROL__RESERVED_31__SHIFT                                        21
#define EMAC_REGS__Q_CONTROL__RESERVED_31__WIDTH                                        11
#define EMAC_REGS__Q_CONTROL__RESERVED_31__MASK                                0xffe00000U
#define EMAC_REGS__Q_CONTROL__RESERVED_31__RESET                                         0
#define EMAC_REGS__Q_CONTROL__RESERVED_31__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffe00000U) >> 21)
#define EMAC_REGS__Q_CONTROL__TYPE                                                uint32_t
#define EMAC_REGS__Q_CONTROL__READ                                             0xffe7ffffU
#define EMAC_REGS__Q_CONTROL__WRITE                                            0xffe7ffffU

#endif /* __Q_CONTROL_MACRO__ */


/* macros for q0_control */
#define EMAC_REGS__INST_Q0_CONTROL__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::q_status */
#ifndef __EMAC_REGS__Q_STATUS_MACRO__
#define __EMAC_REGS__Q_STATUS_MACRO__

/* macros for field frame_received */
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__SHIFT                                       0
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__WIDTH                                       1
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__MASK                              0x00000001U
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__RESET                                       0
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__READ(src)     ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__WRITE(src)    ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__Q_STATUS__FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field rx_used_bit_read */
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__SHIFT                                     1
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__WIDTH                                     1
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__MASK                            0x00000002U
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__RESET                                     0
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__Q_STATUS__RX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field rx_resp_not_ok */
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__SHIFT                                       2
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__WIDTH                                       1
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__MASK                              0x00000004U
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__RESET                                       0
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__Q_STATUS__RX_RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field reserved_3 */
#define EMAC_REGS__Q_STATUS__RESERVED_3__SHIFT                                           3
#define EMAC_REGS__Q_STATUS__RESERVED_3__WIDTH                                           1
#define EMAC_REGS__Q_STATUS__RESERVED_3__MASK                                  0x00000008U
#define EMAC_REGS__Q_STATUS__RESERVED_3__RESET                                           0
#define EMAC_REGS__Q_STATUS__RESERVED_3__READ(src)  (((uint32_t)(src) & 0x00000008U) >> 3)
#define EMAC_REGS__Q_STATUS__RESERVED_3__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__Q_STATUS__RESERVED_3__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field transmit_complete */
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__SHIFT                                    4
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__WIDTH                                    1
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__MASK                           0x00000010U
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__RESET                                    0
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__Q_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field tx_used_bit_read */
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__SHIFT                                     5
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__WIDTH                                     1
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__MASK                            0x00000020U
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__RESET                                     0
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field tx_used_bit_read_midframe */
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__SHIFT                            6
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__WIDTH                            1
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__MASK                   0x00000040U
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__RESET                            0
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__Q_STATUS__TX_USED_BIT_READ_MIDFRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field tx_resp_not_ok */
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__SHIFT                                       7
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__WIDTH                                       1
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__MASK                              0x00000080U
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__RESET                                       0
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__Q_STATUS__TX_RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)

/* macros for field reserved_31_8 */
#define EMAC_REGS__Q_STATUS__RESERVED_31_8__SHIFT                                        8
#define EMAC_REGS__Q_STATUS__RESERVED_31_8__WIDTH                                       24
#define EMAC_REGS__Q_STATUS__RESERVED_31_8__MASK                               0xffffff00U
#define EMAC_REGS__Q_STATUS__RESERVED_31_8__RESET                                        0
#define EMAC_REGS__Q_STATUS__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__Q_STATUS__TYPE                                                 uint32_t
#define EMAC_REGS__Q_STATUS__READ                                              0xffffffffU
#define EMAC_REGS__Q_STATUS__WRITE                                             0xffffffffU
#define EMAC_REGS__Q_STATUS__WOCLR                                             0x000000f7U

#endif /* __Q_STATUS_MACRO__ */


/* macros for q0_status */
#define EMAC_REGS__INST_Q0_STATUS__NUM                                                   1

/* macros for q1_control */
#define EMAC_REGS__INST_Q1_CONTROL__NUM                                                  1

/* macros for q1_status */
#define EMAC_REGS__INST_Q1_STATUS__NUM                                                   1

/* macros for q2_control */
#define EMAC_REGS__INST_Q2_CONTROL__NUM                                                  1

/* macros for q2_status */
#define EMAC_REGS__INST_Q2_STATUS__NUM                                                   1

/* macros for q3_control */
#define EMAC_REGS__INST_Q3_CONTROL__NUM                                                  1

/* macros for q3_status */
#define EMAC_REGS__INST_Q3_STATUS__NUM                                                   1

/* macros for q4_control */
#define EMAC_REGS__INST_Q4_CONTROL__NUM                                                  1

/* macros for q4_status */
#define EMAC_REGS__INST_Q4_STATUS__NUM                                                   1

/* macros for q5_control */
#define EMAC_REGS__INST_Q5_CONTROL__NUM                                                  1

/* macros for q5_status */
#define EMAC_REGS__INST_Q5_STATUS__NUM                                                   1

/* macros for q6_control */
#define EMAC_REGS__INST_Q6_CONTROL__NUM                                                  1

/* macros for q6_status */
#define EMAC_REGS__INST_Q6_STATUS__NUM                                                   1

/* macros for q7_control */
#define EMAC_REGS__INST_Q7_CONTROL__NUM                                                  1

/* macros for q7_status */
#define EMAC_REGS__INST_Q7_STATUS__NUM                                                   1

/* macros for q8_control */
#define EMAC_REGS__INST_Q8_CONTROL__NUM                                                  1

/* macros for q8_status */
#define EMAC_REGS__INST_Q8_STATUS__NUM                                                   1

/* macros for q9_control */
#define EMAC_REGS__INST_Q9_CONTROL__NUM                                                  1

/* macros for q9_status */
#define EMAC_REGS__INST_Q9_STATUS__NUM                                                   1

/* macros for q10_control */
#define EMAC_REGS__INST_Q10_CONTROL__NUM                                                 1

/* macros for q10_status */
#define EMAC_REGS__INST_Q10_STATUS__NUM                                                  1

/* macros for q11_control */
#define EMAC_REGS__INST_Q11_CONTROL__NUM                                                 1

/* macros for q11_status */
#define EMAC_REGS__INST_Q11_STATUS__NUM                                                  1

/* macros for q12_control */
#define EMAC_REGS__INST_Q12_CONTROL__NUM                                                 1

/* macros for q12_status */
#define EMAC_REGS__INST_Q12_STATUS__NUM                                                  1

/* macros for q13_control */
#define EMAC_REGS__INST_Q13_CONTROL__NUM                                                 1

/* macros for q13_status */
#define EMAC_REGS__INST_Q13_STATUS__NUM                                                  1

/* macros for q14_control */
#define EMAC_REGS__INST_Q14_CONTROL__NUM                                                 1

/* macros for q14_status */
#define EMAC_REGS__INST_Q14_STATUS__NUM                                                  1

/* macros for q15_control */
#define EMAC_REGS__INST_Q15_CONTROL__NUM                                                 1

/* macros for q15_status */
#define EMAC_REGS__INST_Q15_STATUS__NUM                                                  1

/* macros for BlueprintGlobalNameSpace::asf_int_status */
#ifndef __EMAC_REGS__ASF_INT_STATUS_MACRO__
#define __EMAC_REGS__ASF_INT_STATUS_MACRO__

/* macros for field asf_sram_corr_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__SHIFT                              0
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__WIDTH                              1
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__MASK                     0x00000001U
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__RESET                            0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field asf_sram_uncorr_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__SHIFT                            1
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__WIDTH                            1
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__MASK                   0x00000002U
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__RESET                          0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field asf_dap_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__SHIFT                                    2
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__WIDTH                                    1
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__MASK                           0x00000004U
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__RESET                                  0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_DAP_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field asf_csr_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__SHIFT                                    3
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__WIDTH                                    1
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__MASK                           0x00000008U
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__RESET                                  0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_CSR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field asf_trans_to_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__SHIFT                               4
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__WIDTH                               1
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__MASK                      0x00000010U
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__RESET                             0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field asf_protocol_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__SHIFT                               5
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__WIDTH                               1
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__MASK                      0x00000020U
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__RESET                             0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field asf_integrity_err */
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__SHIFT                              6
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__WIDTH                              1
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__MASK                     0x00000040U
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__RESET                            0b0
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field reserved_31_7 */
#define EMAC_REGS__ASF_INT_STATUS__RESERVED_31_7__SHIFT                                  7
#define EMAC_REGS__ASF_INT_STATUS__RESERVED_31_7__WIDTH                                 25
#define EMAC_REGS__ASF_INT_STATUS__RESERVED_31_7__MASK                         0xffffff80U
#define EMAC_REGS__ASF_INT_STATUS__RESERVED_31_7__RESET                                  0
#define EMAC_REGS__ASF_INT_STATUS__RESERVED_31_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff80U) >> 7)
#define EMAC_REGS__ASF_INT_STATUS__TYPE                                           uint32_t
#define EMAC_REGS__ASF_INT_STATUS__READ                                        0xffffffffU
#define EMAC_REGS__ASF_INT_STATUS__WRITE                                       0xffffffffU
#define EMAC_REGS__ASF_INT_STATUS__WOCLR                                       0x0000007fU

#endif /* __ASF_INT_STATUS_MACRO__ */


/* macros for asf_int_status */
#define EMAC_REGS__INST_ASF_INT_STATUS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::asf_int_raw_status */
#ifndef __EMAC_REGS__ASF_INT_RAW_STATUS_MACRO__
#define __EMAC_REGS__ASF_INT_RAW_STATUS_MACRO__

/* macros for field asf_sram_corr_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__SHIFT                          0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__WIDTH                          1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__MASK                 0x00000001U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__RESET                        0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field asf_sram_uncorr_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__SHIFT                        1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__WIDTH                        1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__MASK               0x00000002U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__RESET                      0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field asf_dap_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__SHIFT                                2
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__WIDTH                                1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__MASK                       0x00000004U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__RESET                              0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field asf_csr_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__SHIFT                                3
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__WIDTH                                1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__MASK                       0x00000008U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__RESET                              0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field asf_trans_to_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__SHIFT                           4
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__WIDTH                           1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__MASK                  0x00000010U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__RESET                         0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field asf_protocol_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__SHIFT                           5
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__WIDTH                           1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__MASK                  0x00000020U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__RESET                         0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field asf_integrity_err */
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__SHIFT                          6
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__WIDTH                          1
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__MASK                 0x00000040U
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__RESET                        0b0
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field reserved_31_7 */
#define EMAC_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7__SHIFT                              7
#define EMAC_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7__WIDTH                             25
#define EMAC_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7__MASK                     0xffffff80U
#define EMAC_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7__RESET                              0
#define EMAC_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff80U) >> 7)
#define EMAC_REGS__ASF_INT_RAW_STATUS__TYPE                                       uint32_t
#define EMAC_REGS__ASF_INT_RAW_STATUS__READ                                    0xffffffffU
#define EMAC_REGS__ASF_INT_RAW_STATUS__WRITE                                   0xffffffffU
#define EMAC_REGS__ASF_INT_RAW_STATUS__WOCLR                                   0x0000007fU

#endif /* __ASF_INT_RAW_STATUS_MACRO__ */


/* macros for asf_int_raw_status */
#define EMAC_REGS__INST_ASF_INT_RAW_STATUS__NUM                                          1

/* macros for BlueprintGlobalNameSpace::asf_int_mask */
#ifndef __EMAC_REGS__ASF_INT_MASK_MACRO__
#define __EMAC_REGS__ASF_INT_MASK_MACRO__

/* macros for field asf_sram_corr_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__SHIFT                           0
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__WIDTH                           1
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__MASK                  0x00000001U
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__RESET                         0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field asf_sram_uncorr_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__SHIFT                         1
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__WIDTH                         1
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__MASK                0x00000002U
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__RESET                       0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field asf_dap_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__SHIFT                                 2
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__WIDTH                                 1
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__MASK                        0x00000004U
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__RESET                               0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field asf_csr_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__SHIFT                                 3
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__WIDTH                                 1
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__MASK                        0x00000008U
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__RESET                               0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field asf_trans_to_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__SHIFT                            4
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__WIDTH                            1
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__MASK                   0x00000010U
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__RESET                          0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field asf_protocol_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__SHIFT                            5
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__WIDTH                            1
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__MASK                   0x00000020U
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__RESET                          0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field asf_integrity_err_mask */
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__SHIFT                           6
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__WIDTH                           1
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__MASK                  0x00000040U
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__RESET                         0b1
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_31_7 */
#define EMAC_REGS__ASF_INT_MASK__RESERVED_31_7__SHIFT                                    7
#define EMAC_REGS__ASF_INT_MASK__RESERVED_31_7__WIDTH                                   25
#define EMAC_REGS__ASF_INT_MASK__RESERVED_31_7__MASK                           0xffffff80U
#define EMAC_REGS__ASF_INT_MASK__RESERVED_31_7__RESET                                    0
#define EMAC_REGS__ASF_INT_MASK__RESERVED_31_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff80U) >> 7)
#define EMAC_REGS__ASF_INT_MASK__TYPE                                             uint32_t
#define EMAC_REGS__ASF_INT_MASK__READ                                          0xffffffffU
#define EMAC_REGS__ASF_INT_MASK__WRITE                                         0xffffffffU

#endif /* __ASF_INT_MASK_MACRO__ */


/* macros for asf_int_mask */
#define EMAC_REGS__INST_ASF_INT_MASK__NUM                                                1

/* macros for BlueprintGlobalNameSpace::asf_int_test */
#ifndef __EMAC_REGS__ASF_INT_TEST_MACRO__
#define __EMAC_REGS__ASF_INT_TEST_MACRO__

/* macros for field asf_sram_corr_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__SHIFT                           0
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__WIDTH                           1
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__MASK                  0x00000001U
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__RESET                         0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field asf_sram_uncorr_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__SHIFT                         1
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__WIDTH                         1
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__MASK                0x00000002U
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__RESET                       0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field asf_dap_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__SHIFT                                 2
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__WIDTH                                 1
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__MASK                        0x00000004U
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__RESET                               0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field asf_csr_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__SHIFT                                 3
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__WIDTH                                 1
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__MASK                        0x00000008U
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__RESET                               0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field asf_trans_to_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__SHIFT                            4
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__WIDTH                            1
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__MASK                   0x00000010U
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__RESET                          0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field asf_protocol_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__SHIFT                            5
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__WIDTH                            1
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__MASK                   0x00000020U
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__RESET                          0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field asf_integrity_err_test */
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__SHIFT                           6
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__WIDTH                           1
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__MASK                  0x00000040U
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__RESET                         0b0
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_31_7 */
#define EMAC_REGS__ASF_INT_TEST__RESERVED_31_7__SHIFT                                    7
#define EMAC_REGS__ASF_INT_TEST__RESERVED_31_7__WIDTH                                   25
#define EMAC_REGS__ASF_INT_TEST__RESERVED_31_7__MASK                           0xffffff80U
#define EMAC_REGS__ASF_INT_TEST__RESERVED_31_7__RESET                                    0
#define EMAC_REGS__ASF_INT_TEST__RESERVED_31_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff80U) >> 7)
#define EMAC_REGS__ASF_INT_TEST__TYPE                                             uint32_t
#define EMAC_REGS__ASF_INT_TEST__READ                                          0xffffff80U
#define EMAC_REGS__ASF_INT_TEST__WRITE                                         0xffffff80U

#endif /* __ASF_INT_TEST_MACRO__ */


/* macros for asf_int_test */
#define EMAC_REGS__INST_ASF_INT_TEST__NUM                                                1

/* macros for BlueprintGlobalNameSpace::asf_fatal_nonfatal_select */
#ifndef __EMAC_REGS__ASF_FATAL_NONFATAL_SELECT_MACRO__
#define __EMAC_REGS__ASF_FATAL_NONFATAL_SELECT_MACRO__

/* macros for field asf_sram_corr_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__SHIFT                   0
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__WIDTH                   1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__MASK          0x00000001U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__RESET                 0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field asf_sram_uncorr_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__SHIFT                 1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__WIDTH                 1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__MASK        0x00000002U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__RESET               0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field asf_dap_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__SHIFT                         2
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__WIDTH                         1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__MASK                0x00000004U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__RESET                       0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field asf_csr_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__SHIFT                         3
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__WIDTH                         1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__MASK                0x00000008U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__RESET                       0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field asf_trans_to_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__SHIFT                    4
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__WIDTH                    1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__MASK           0x00000010U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__RESET                  0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field asf_protocol_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__SHIFT                    5
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__WIDTH                    1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__MASK           0x00000020U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__RESET                  0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field asf_integrity_err */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__SHIFT                   6
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__WIDTH                   1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__MASK          0x00000040U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__RESET                 0b1
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_31_7 */
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7__SHIFT                       7
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7__WIDTH                      25
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7__MASK              0xffffff80U
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7__RESET                       0
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff80U) >> 7)
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__TYPE                                uint32_t
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__READ                             0xffffffffU
#define EMAC_REGS__ASF_FATAL_NONFATAL_SELECT__WRITE                            0xffffffffU

#endif /* __ASF_FATAL_NONFATAL_SELECT_MACRO__ */


/* macros for asf_fatal_nonfatal_select */
#define EMAC_REGS__INST_ASF_FATAL_NONFATAL_SELECT__NUM                                   1

/* macros for BlueprintGlobalNameSpace::asf_sram_corr_fault_status */
#ifndef __EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS_MACRO__
#define __EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS_MACRO__

/* macros for field asf_sram_corr_fault_addr */
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR__SHIFT           0
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR__WIDTH          24
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR__MASK  0x00ffffffU
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR__RESET           0
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00ffffffU)

/* macros for field asf_sram_corr_fault_inst */
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST__SHIFT          24
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST__WIDTH           8
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST__MASK  0xff000000U
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST__RESET           0
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__TYPE                               uint32_t
#define EMAC_REGS__ASF_SRAM_CORR_FAULT_STATUS__READ                            0xffffffffU

#endif /* __ASF_SRAM_CORR_FAULT_STATUS_MACRO__ */


/* macros for asf_sram_corr_fault_status */
#define EMAC_REGS__INST_ASF_SRAM_CORR_FAULT_STATUS__NUM                                  1

/* macros for BlueprintGlobalNameSpace::asf_sram_uncorr_fault_status */
#ifndef __EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS_MACRO__
#define __EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS_MACRO__

/* macros for field asf_sram_uncorr_fault_addr */
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR__SHIFT       0
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR__WIDTH      24
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR__MASK \
                    0x00ffffffU
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR__RESET       0
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00ffffffU)

/* macros for field asf_sram_uncorr_fault_inst */
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST__SHIFT      24
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST__WIDTH       8
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST__MASK \
                    0xff000000U
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST__RESET       0
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__TYPE                             uint32_t
#define EMAC_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__READ                          0xffffffffU

#endif /* __ASF_SRAM_UNCORR_FAULT_STATUS_MACRO__ */


/* macros for asf_sram_uncorr_fault_status */
#define EMAC_REGS__INST_ASF_SRAM_UNCORR_FAULT_STATUS__NUM                                1

/* macros for BlueprintGlobalNameSpace::asf_sram_fault_stats */
#ifndef __EMAC_REGS__ASF_SRAM_FAULT_STATS_MACRO__
#define __EMAC_REGS__ASF_SRAM_FAULT_STATS_MACRO__

/* macros for field asf_sram_fault_corr_stats */
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__SHIFT                0
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__WIDTH               16
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__MASK       0x0000ffffU
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__RESET                0
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_31_16 */
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__RESERVED_31_16__SHIFT                          16
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__RESERVED_31_16__WIDTH                          16
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__RESERVED_31_16__MASK                  0xffff0000U
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__RESERVED_31_16__RESET                           0
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__RESERVED_31_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffff0000U) >> 16)
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__TYPE                                     uint32_t
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__READ                                  0xffffffffU
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__WRITE                                 0xffffffffU
#define EMAC_REGS__ASF_SRAM_FAULT_STATS__WOCLR                                 0x0000ffffU

#endif /* __ASF_SRAM_FAULT_STATS_MACRO__ */


/* macros for asf_sram_fault_stats */
#define EMAC_REGS__INST_ASF_SRAM_FAULT_STATS__NUM                                        1

/* macros for BlueprintGlobalNameSpace::asf_trans_to_ctrl */
#ifndef __EMAC_REGS__ASF_TRANS_TO_CTRL_MACRO__
#define __EMAC_REGS__ASF_TRANS_TO_CTRL_MACRO__

/* macros for field asf_trans_to_ctrl */
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__SHIFT                           0
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__WIDTH                          16
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__MASK                  0x0000ffffU
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__RESET                           0
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field reserved_30_16 */
#define EMAC_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16__SHIFT                             16
#define EMAC_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16__WIDTH                             15
#define EMAC_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16__MASK                     0x7fff0000U
#define EMAC_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16__RESET                              0
#define EMAC_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7fff0000U) >> 16)

/* macros for field asf_trans_to_en */
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__SHIFT                            31
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__WIDTH                             1
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__MASK                    0x80000000U
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__RESET                             0
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__ASF_TRANS_TO_CTRL__TYPE                                        uint32_t
#define EMAC_REGS__ASF_TRANS_TO_CTRL__READ                                     0xffffffffU
#define EMAC_REGS__ASF_TRANS_TO_CTRL__WRITE                                    0xffffffffU

#endif /* __ASF_TRANS_TO_CTRL_MACRO__ */


/* macros for asf_trans_to_ctrl */
#define EMAC_REGS__INST_ASF_TRANS_TO_CTRL__NUM                                           1

/* macros for BlueprintGlobalNameSpace::asf_trans_to_fault_mask */
#ifndef __EMAC_REGS__ASF_TRANS_TO_FAULT_MASK_MACRO__
#define __EMAC_REGS__ASF_TRANS_TO_FAULT_MASK_MACRO__

/* macros for field mac_tx_to_mask */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__SHIFT                        0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__WIDTH                        1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__MASK               0x00000001U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__RESET                      0b1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_TX_TO_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field mac_rx_to_mask */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__SHIFT                        1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__WIDTH                        1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__MASK               0x00000002U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__RESET                      0b1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__MAC_RX_TO_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field dma_tx_to_mask */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__SHIFT                        2
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__WIDTH                        1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__MASK               0x00000004U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__RESET                      0b1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_TX_TO_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field dma_rx_to_mask */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__SHIFT                        3
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__WIDTH                        1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__MASK               0x00000008U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__RESET                      0b1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__DMA_RX_TO_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field host_trans_to_mask */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__SHIFT                    4
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__WIDTH                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__MASK           0x00000010U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__RESET                  0b1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__HOST_TRANS_TO_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field reserved_31_5 */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_5__SHIFT                         5
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_5__WIDTH                        27
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_5__MASK                0xffffffe0U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_5__RESET                         0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_5__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffe0U) >> 5)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__TYPE                                  uint32_t
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__READ                               0xffffffffU
#define EMAC_REGS__ASF_TRANS_TO_FAULT_MASK__WRITE                              0xffffffffU

#endif /* __ASF_TRANS_TO_FAULT_MASK_MACRO__ */


/* macros for asf_trans_to_fault_mask */
#define EMAC_REGS__INST_ASF_TRANS_TO_FAULT_MASK__NUM                                     1

/* macros for BlueprintGlobalNameSpace::asf_trans_to_fault_status */
#ifndef __EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS_MACRO__
#define __EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS_MACRO__

/* macros for field mac_tx_to_status */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__SHIFT                    0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__WIDTH                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__MASK           0x00000001U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__RESET                  0b0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_TX_TO_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field mac_rx_to_status */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__SHIFT                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__WIDTH                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__MASK           0x00000002U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__RESET                  0b0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__MAC_RX_TO_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field dma_tx_to_status */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__SHIFT                    2
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__WIDTH                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__MASK           0x00000004U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__RESET                  0b0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_TX_TO_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field dma_rx_to_status */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__SHIFT                    3
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__WIDTH                    1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__MASK           0x00000008U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__RESET                  0b0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__DMA_RX_TO_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field host_trans_to_status */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__SHIFT                4
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__WIDTH                1
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__MASK       0x00000010U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__RESET              0b0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__HOST_TRANS_TO_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field reserved_31_5 */
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_5__SHIFT                       5
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_5__WIDTH                      27
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_5__MASK              0xffffffe0U
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_5__RESET                       0
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_5__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffe0U) >> 5)
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__TYPE                                uint32_t
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__READ                             0xffffffffU
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__WRITE                            0xffffffffU
#define EMAC_REGS__ASF_TRANS_TO_FAULT_STATUS__WOCLR                            0x0000001fU

#endif /* __ASF_TRANS_TO_FAULT_STATUS_MACRO__ */


/* macros for asf_trans_to_fault_status */
#define EMAC_REGS__INST_ASF_TRANS_TO_FAULT_STATUS__NUM                                   1

/* macros for BlueprintGlobalNameSpace::asf_protocol_fault_mask */
#ifndef __EMAC_REGS__ASF_PROTOCOL_FAULT_MASK_MACRO__
#define __EMAC_REGS__ASF_PROTOCOL_FAULT_MASK_MACRO__

/* macros for field rx_crc_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__SHIFT                       0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__WIDTH                       1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__MASK              0x00000001U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__RESET                     0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_CRC_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rx_short_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__SHIFT                     1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__WIDTH                     1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__MASK            0x00000002U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__RESET                   0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SHORT_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field rx_long_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__SHIFT                      2
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__WIDTH                      1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__MASK             0x00000004U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__RESET                    0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LONG_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field rx_symbol_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__SHIFT                    3
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__WIDTH                    1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__MASK           0x00000008U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__RESET                  0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_SYMBOL_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field rx_length_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__SHIFT                    4
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__WIDTH                    1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__MASK           0x00000010U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__RESET                  0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_LENGTH_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field rx_ip_ck_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__SHIFT                     5
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__WIDTH                     1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__MASK            0x00000020U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__RESET                   0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_IP_CK_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field rx_tcp_ck_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__SHIFT                    6
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__WIDTH                    1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__MASK           0x00000040U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__RESET                  0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_TCP_CK_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field rx_udp_ck_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__SHIFT                    7
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__WIDTH                    1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__MASK           0x00000080U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__RESET                  0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_UDP_CK_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field tx_too_many_retries_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__SHIFT              8
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__WIDTH              1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__MASK     0x00000100U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__RESET            0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_TOO_MANY_RETRIES_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_15_9__SHIFT                         9
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_15_9__WIDTH                         7
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_15_9__MASK                0x0000fe00U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_15_9__RESET                         0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field tx_underrun_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__SHIFT                     16
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__WIDTH                      1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__MASK             0x00010000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__RESET                    0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_UNDERRUN_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field tx_buff_ex_mid_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__SHIFT                  17
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__WIDTH                   1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__MASK          0x00020000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__RESET                 0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_BUFF_EX_MID_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field tx_hresp_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__SHIFT                    18
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__WIDTH                     1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__MASK            0x00040000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__RESET                   0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TX_HRESP_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field rx_hresp_err_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__SHIFT                    19
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__WIDTH                     1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__MASK            0x00080000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__RESET                   0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_HRESP_ERR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field rx_overflow_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__SHIFT                     20
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__WIDTH                      1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__MASK             0x00100000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__RESET                    0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_OVERFLOW_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field rx_dma_pkt_flush_mask */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__SHIFT                21
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__WIDTH                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__MASK        0x00200000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__RESET               0b1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RX_DMA_PKT_FLUSH_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field reserved_31_22 */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_22__SHIFT                       22
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_22__WIDTH                       10
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_22__MASK               0xffc00000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_22__RESET                        0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_22__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffc00000U) >> 22)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__TYPE                                  uint32_t
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__READ                               0xffffffffU
#define EMAC_REGS__ASF_PROTOCOL_FAULT_MASK__WRITE                              0xffffffffU

#endif /* __ASF_PROTOCOL_FAULT_MASK_MACRO__ */


/* macros for asf_protocol_fault_mask */
#define EMAC_REGS__INST_ASF_PROTOCOL_FAULT_MASK__NUM                                     1

/* macros for BlueprintGlobalNameSpace::asf_protocol_fault_status */
#ifndef __EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS_MACRO__
#define __EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS_MACRO__

/* macros for field rx_crc_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__SHIFT                   0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__WIDTH                   1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__MASK          0x00000001U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__RESET                 0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_CRC_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field rx_short_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__SHIFT                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__WIDTH                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__MASK        0x00000002U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__RESET               0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SHORT_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field rx_long_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__SHIFT                  2
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__WIDTH                  1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__MASK         0x00000004U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__RESET                0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LONG_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field rx_symbol_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__SHIFT                3
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__WIDTH                1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__MASK       0x00000008U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__RESET              0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_SYMBOL_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field rx_length_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__SHIFT                4
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__WIDTH                1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__MASK       0x00000010U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__RESET              0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_LENGTH_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field rx_ip_ck_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__SHIFT                 5
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__WIDTH                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__MASK        0x00000020U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__RESET               0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_IP_CK_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field rx_tcp_ck_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__SHIFT                6
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__WIDTH                1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__MASK       0x00000040U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__RESET              0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_TCP_CK_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field rx_udp_ck_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__SHIFT                7
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__WIDTH                1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__MASK       0x00000080U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__RESET              0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_UDP_CK_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)

/* macros for field tx_too_many_retries_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__SHIFT          8
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__WIDTH          1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__MASK 0x00000100U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__RESET        0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_TOO_MANY_RETRIES_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)

/* macros for field reserved_15_9 */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_15_9__SHIFT                       9
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_15_9__WIDTH                       7
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_15_9__MASK              0x0000fe00U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_15_9__RESET                       0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_15_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000fe00U) >> 9)

/* macros for field tx_underrun_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__SHIFT                 16
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__WIDTH                  1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__MASK         0x00010000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__RESET                0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_UNDERRUN_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)

/* macros for field tx_buff_ex_mid_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__SHIFT              17
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__WIDTH               1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__MASK      0x00020000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__RESET             0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00020000U) >> 17)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_BUFF_EX_MID_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)

/* macros for field tx_hresp_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__SHIFT                18
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__WIDTH                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__MASK        0x00040000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__RESET               0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00040000U) >> 18)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TX_HRESP_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)

/* macros for field rx_hresp_err_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__SHIFT                19
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__WIDTH                 1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__MASK        0x00080000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__RESET               0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_HRESP_ERR_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)

/* macros for field rx_overflow_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__SHIFT                 20
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__WIDTH                  1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__MASK         0x00100000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__RESET                0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_OVERFLOW_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)

/* macros for field rx_dma_pkt_flush_status */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__SHIFT            21
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__WIDTH             1
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__MASK    0x00200000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__RESET           0b0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RX_DMA_PKT_FLUSH_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)

/* macros for field reserved_31_22 */
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_31_22__SHIFT                     22
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_31_22__WIDTH                     10
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_31_22__MASK             0xffc00000U
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_31_22__RESET                      0
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_31_22__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffc00000U) >> 22)
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__TYPE                                uint32_t
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__READ                             0xffffffffU
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__WRITE                            0xffffffffU
#define EMAC_REGS__ASF_PROTOCOL_FAULT_STATUS__WOCLR                            0x003f01ffU

#endif /* __ASF_PROTOCOL_FAULT_STATUS_MACRO__ */


/* macros for asf_protocol_fault_status */
#define EMAC_REGS__INST_ASF_PROTOCOL_FAULT_STATUS__NUM                                   1

/* macros for BlueprintGlobalNameSpace::mmsl_control */
#ifndef __EMAC_REGS__MMSL_CONTROL_MACRO__
#define __EMAC_REGS__MMSL_CONTROL_MACRO__

/* macros for field add_frag_size */
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__SHIFT                                    0
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__WIDTH                                    2
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__MASK                           0x00000003U
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__RESET                                    0
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__READ(src)  ((uint32_t)(src) & 0x00000003U)
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__WRITE(src) ((uint32_t)(src) & 0x00000003U)
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((uint32_t)(src) &\
                    0x00000003U)
#define EMAC_REGS__MMSL_CONTROL__ADD_FRAG_SIZE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000003U)))

/* macros for field verify_disable */
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__SHIFT                                   2
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__WIDTH                                   1
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__MASK                          0x00000004U
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__RESET                                   0
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__MMSL_CONTROL__VERIFY_DISABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field pre_enable */
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__SHIFT                                       3
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__WIDTH                                       1
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__MASK                              0x00000008U
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__RESET                                       0
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__MMSL_CONTROL__PRE_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field restart_ver */
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__SHIFT                                      4
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__WIDTH                                      1
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__MASK                             0x00000010U
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__RESET                                      0
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__MMSL_CONTROL__RESTART_VER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field route_rx_to_pmac */
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__SHIFT                                 5
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__WIDTH                                 1
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__MASK                        0x00000020U
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__RESET                                 1
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_CONTROL__ROUTE_RX_TO_PMAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field mmsl_debug_mode */
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__SHIFT                                  6
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__WIDTH                                  1
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__MASK                         0x00000040U
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__RESET                                  0
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__MMSL_CONTROL__MMSL_DEBUG_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field invert_mcrc */
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__SHIFT                                      7
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__WIDTH                                      1
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__MASK                             0x00000080U
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__RESET                                      0
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__MMSL_CONTROL__INVERT_MCRC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field mmsl_bypass */
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__SHIFT                                      8
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__WIDTH                                      1
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__MASK                             0x00000100U
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__RESET                                      1
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__MMSL_CONTROL__MMSL_BYPASS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field reserved_31_9 */
#define EMAC_REGS__MMSL_CONTROL__RESERVED_31_9__SHIFT                                    9
#define EMAC_REGS__MMSL_CONTROL__RESERVED_31_9__WIDTH                                   23
#define EMAC_REGS__MMSL_CONTROL__RESERVED_31_9__MASK                           0xfffffe00U
#define EMAC_REGS__MMSL_CONTROL__RESERVED_31_9__RESET                                    0
#define EMAC_REGS__MMSL_CONTROL__RESERVED_31_9__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffe00U) >> 9)
#define EMAC_REGS__MMSL_CONTROL__TYPE                                             uint32_t
#define EMAC_REGS__MMSL_CONTROL__READ                                          0xffffffefU
#define EMAC_REGS__MMSL_CONTROL__WRITE                                         0xffffffefU

#endif /* __MMSL_CONTROL_MACRO__ */


/* macros for mmsl_control */
#define EMAC_REGS__INST_MMSL_CONTROL__NUM                                                1

/* macros for BlueprintGlobalNameSpace::mmsl_status */
#ifndef __EMAC_REGS__MMSL_STATUS_MACRO__
#define __EMAC_REGS__MMSL_STATUS_MACRO__

/* macros for field pre_active */
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__SHIFT                                        0
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__WIDTH                                        1
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__MASK                               0x00000001U
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__RESET                                        0
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__READ(src)      ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__MMSL_STATUS__PRE_ACTIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field respond_status */
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__SHIFT                                    1
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__WIDTH                                    1
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__MASK                           0x00000002U
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__RESET                                    0
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__MMSL_STATUS__RESPOND_STATUS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field verify_status */
#define EMAC_REGS__MMSL_STATUS__VERIFY_STATUS__SHIFT                                     2
#define EMAC_REGS__MMSL_STATUS__VERIFY_STATUS__WIDTH                                     3
#define EMAC_REGS__MMSL_STATUS__VERIFY_STATUS__MASK                            0x0000001cU
#define EMAC_REGS__MMSL_STATUS__VERIFY_STATUS__RESET                                     0
#define EMAC_REGS__MMSL_STATUS__VERIFY_STATUS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000001cU) >> 2)

/* macros for field rcv_r_error */
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__SHIFT                                       5
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__WIDTH                                       1
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__MASK                              0x00000020U
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__RESET                                       0
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_STATUS__RCV_R_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field rcv_v_error */
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__SHIFT                                       6
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__WIDTH                                       1
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__MASK                              0x00000040U
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__RESET                                       0
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__MMSL_STATUS__RCV_V_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field smds_error */
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__SHIFT                                        7
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__WIDTH                                        1
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__MASK                               0x00000080U
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__RESET                                        0
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__MMSL_STATUS__SMDS_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field smdc_error */
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__SHIFT                                        8
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__WIDTH                                        1
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__MASK                               0x00000100U
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__RESET                                        0
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__MMSL_STATUS__SMDC_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field frer_count_err */
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__SHIFT                                    9
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__WIDTH                                    1
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__MASK                           0x00000200U
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__RESET                                    0
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__MMSL_STATUS__FRER_COUNT_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field smd_error */
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__SHIFT                                        10
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__WIDTH                                         1
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__MASK                                0x00000400U
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__RESET                                         0
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__MMSL_STATUS__SMD_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field reserved_31_11 */
#define EMAC_REGS__MMSL_STATUS__RESERVED_31_11__SHIFT                                   11
#define EMAC_REGS__MMSL_STATUS__RESERVED_31_11__WIDTH                                   21
#define EMAC_REGS__MMSL_STATUS__RESERVED_31_11__MASK                           0xfffff800U
#define EMAC_REGS__MMSL_STATUS__RESERVED_31_11__RESET                                    0
#define EMAC_REGS__MMSL_STATUS__RESERVED_31_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff800U) >> 11)
#define EMAC_REGS__MMSL_STATUS__TYPE                                              uint32_t
#define EMAC_REGS__MMSL_STATUS__READ                                           0xffffffffU
#define EMAC_REGS__MMSL_STATUS__RCLR                                           0x000007e0U

#endif /* __MMSL_STATUS_MACRO__ */


/* macros for mmsl_status */
#define EMAC_REGS__INST_MMSL_STATUS__NUM                                                 1

/* macros for BlueprintGlobalNameSpace::mmsl_err_stats */
#ifndef __EMAC_REGS__MMSL_ERR_STATS_MACRO__
#define __EMAC_REGS__MMSL_ERR_STATS_MACRO__

/* macros for field ass_error_count */
#define EMAC_REGS__MMSL_ERR_STATS__ASS_ERROR_COUNT__SHIFT                                0
#define EMAC_REGS__MMSL_ERR_STATS__ASS_ERROR_COUNT__WIDTH                                8
#define EMAC_REGS__MMSL_ERR_STATS__ASS_ERROR_COUNT__MASK                       0x000000ffU
#define EMAC_REGS__MMSL_ERR_STATS__ASS_ERROR_COUNT__RESET                                0
#define EMAC_REGS__MMSL_ERR_STATS__ASS_ERROR_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field reserved_15_8 */
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_15_8__SHIFT                                  8
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_15_8__WIDTH                                  8
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_15_8__MASK                         0x0000ff00U
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_15_8__RESET                                  0
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_15_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field smd_err_count */
#define EMAC_REGS__MMSL_ERR_STATS__SMD_ERR_COUNT__SHIFT                                 16
#define EMAC_REGS__MMSL_ERR_STATS__SMD_ERR_COUNT__WIDTH                                  8
#define EMAC_REGS__MMSL_ERR_STATS__SMD_ERR_COUNT__MASK                         0x00ff0000U
#define EMAC_REGS__MMSL_ERR_STATS__SMD_ERR_COUNT__RESET                                  0
#define EMAC_REGS__MMSL_ERR_STATS__SMD_ERR_COUNT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field reserved_31_24 */
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_31_24__SHIFT                                24
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_31_24__WIDTH                                 8
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_31_24__MASK                        0xff000000U
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_31_24__RESET                                 0
#define EMAC_REGS__MMSL_ERR_STATS__RESERVED_31_24__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__MMSL_ERR_STATS__TYPE                                           uint32_t
#define EMAC_REGS__MMSL_ERR_STATS__READ                                        0xffffffffU
#define EMAC_REGS__MMSL_ERR_STATS__RCLR                                        0x00ff00ffU

#endif /* __MMSL_ERR_STATS_MACRO__ */


/* macros for mmsl_err_stats */
#define EMAC_REGS__INST_MMSL_ERR_STATS__NUM                                              1

/* macros for BlueprintGlobalNameSpace::mmsl_ass_ok_count */
#ifndef __EMAC_REGS__MMSL_ASS_OK_COUNT_MACRO__
#define __EMAC_REGS__MMSL_ASS_OK_COUNT_MACRO__

/* macros for field ass_ok_count */
#define EMAC_REGS__MMSL_ASS_OK_COUNT__ASS_OK_COUNT__SHIFT                                0
#define EMAC_REGS__MMSL_ASS_OK_COUNT__ASS_OK_COUNT__WIDTH                               17
#define EMAC_REGS__MMSL_ASS_OK_COUNT__ASS_OK_COUNT__MASK                       0x0001ffffU
#define EMAC_REGS__MMSL_ASS_OK_COUNT__ASS_OK_COUNT__RESET                                0
#define EMAC_REGS__MMSL_ASS_OK_COUNT__ASS_OK_COUNT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0001ffffU)

/* macros for field reserved_31_17 */
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RESERVED_31_17__SHIFT                             17
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RESERVED_31_17__WIDTH                             15
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RESERVED_31_17__MASK                     0xfffe0000U
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RESERVED_31_17__RESET                              0
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__MMSL_ASS_OK_COUNT__TYPE                                        uint32_t
#define EMAC_REGS__MMSL_ASS_OK_COUNT__READ                                     0xffffffffU
#define EMAC_REGS__MMSL_ASS_OK_COUNT__RCLR                                     0x0001ffffU

#endif /* __MMSL_ASS_OK_COUNT_MACRO__ */


/* macros for mmsl_ass_ok_count */
#define EMAC_REGS__INST_MMSL_ASS_OK_COUNT__NUM                                           1

/* macros for BlueprintGlobalNameSpace::mmsl_frag_count_rx */
#ifndef __EMAC_REGS__MMSL_FRAG_COUNT_RX_MACRO__
#define __EMAC_REGS__MMSL_FRAG_COUNT_RX_MACRO__

/* macros for field frag_count_rx */
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__FRAG_COUNT_RX__SHIFT                              0
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__FRAG_COUNT_RX__WIDTH                             17
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__FRAG_COUNT_RX__MASK                     0x0001ffffU
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__FRAG_COUNT_RX__RESET                              0
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__FRAG_COUNT_RX__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0001ffffU)

/* macros for field reserved_31_17 */
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RESERVED_31_17__SHIFT                            17
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RESERVED_31_17__WIDTH                            15
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RESERVED_31_17__MASK                    0xfffe0000U
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RESERVED_31_17__RESET                             0
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__TYPE                                       uint32_t
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__READ                                    0xffffffffU
#define EMAC_REGS__MMSL_FRAG_COUNT_RX__RCLR                                    0x0001ffffU

#endif /* __MMSL_FRAG_COUNT_RX_MACRO__ */


/* macros for mmsl_frag_count_rx */
#define EMAC_REGS__INST_MMSL_FRAG_COUNT_RX__NUM                                          1

/* macros for BlueprintGlobalNameSpace::mmsl_frag_count_tx */
#ifndef __EMAC_REGS__MMSL_FRAG_COUNT_TX_MACRO__
#define __EMAC_REGS__MMSL_FRAG_COUNT_TX_MACRO__

/* macros for field frag_count_tx */
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__FRAG_COUNT_TX__SHIFT                              0
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__FRAG_COUNT_TX__WIDTH                             17
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__FRAG_COUNT_TX__MASK                     0x0001ffffU
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__FRAG_COUNT_TX__RESET                              0
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__FRAG_COUNT_TX__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0001ffffU)

/* macros for field reserved_31_17 */
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RESERVED_31_17__SHIFT                            17
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RESERVED_31_17__WIDTH                            15
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RESERVED_31_17__MASK                    0xfffe0000U
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RESERVED_31_17__RESET                             0
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__TYPE                                       uint32_t
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__READ                                    0xffffffffU
#define EMAC_REGS__MMSL_FRAG_COUNT_TX__RCLR                                    0x0001ffffU

#endif /* __MMSL_FRAG_COUNT_TX_MACRO__ */


/* macros for mmsl_frag_count_tx */
#define EMAC_REGS__INST_MMSL_FRAG_COUNT_TX__NUM                                          1

/* macros for BlueprintGlobalNameSpace::mmsl_int_status */
#ifndef __EMAC_REGS__MMSL_INT_STATUS_MACRO__
#define __EMAC_REGS__MMSL_INT_STATUS_MACRO__

/* macros for field rcv_r_err */
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__SHIFT                                     0
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__WIDTH                                     1
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__MASK                            0x00000001U
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__RESET                                   0b0
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__READ(src)   ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__WRITE(src)  ((uint32_t)(src) & 0x00000001U)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_R_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rcv_v_err */
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__SHIFT                                     1
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__WIDTH                                     1
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__MASK                            0x00000002U
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__RESET                                   0b0
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__MMSL_INT_STATUS__RCV_V_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field smds_err */
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__SHIFT                                      2
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__WIDTH                                      1
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__MASK                             0x00000004U
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__RESET                                    0b0
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__MMSL_INT_STATUS__SMDS_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field smdc_err */
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__SHIFT                                      3
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__WIDTH                                      1
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__MASK                             0x00000008U
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__RESET                                    0b0
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__MMSL_INT_STATUS__SMDC_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field fr_count_err */
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__SHIFT                                  4
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__WIDTH                                  1
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__MASK                         0x00000010U
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__RESET                                0b0
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__MMSL_INT_STATUS__FR_COUNT_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field smd_err */
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__SHIFT                                       5
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__WIDTH                                       1
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__MASK                              0x00000020U
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__RESET                                     0b0
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_INT_STATUS__SMD_ERR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__MMSL_INT_STATUS__RESERVED_31_6__SHIFT                                 6
#define EMAC_REGS__MMSL_INT_STATUS__RESERVED_31_6__WIDTH                                26
#define EMAC_REGS__MMSL_INT_STATUS__RESERVED_31_6__MASK                        0xffffffc0U
#define EMAC_REGS__MMSL_INT_STATUS__RESERVED_31_6__RESET                                 0
#define EMAC_REGS__MMSL_INT_STATUS__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__MMSL_INT_STATUS__TYPE                                          uint32_t
#define EMAC_REGS__MMSL_INT_STATUS__READ                                       0xffffffffU
#define EMAC_REGS__MMSL_INT_STATUS__RCLR                                       0x0000003fU
#define EMAC_REGS__MMSL_INT_STATUS__WRITE                                      0xffffffffU

#endif /* __MMSL_INT_STATUS_MACRO__ */


/* macros for mmsl_int_status */
#define EMAC_REGS__INST_MMSL_INT_STATUS__NUM                                             1

/* macros for BlueprintGlobalNameSpace::mmsl_int_enable */
#ifndef __EMAC_REGS__MMSL_INT_ENABLE_MACRO__
#define __EMAC_REGS__MMSL_INT_ENABLE_MACRO__

/* macros for field rcv_r_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__SHIFT                            0
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__WIDTH                            1
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__MASK                   0x00000001U
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__RESET                          0b0
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_R_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rcv_v_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__SHIFT                            1
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__WIDTH                            1
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__MASK                   0x00000002U
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__RESET                          0b0
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__MMSL_INT_ENABLE__RCV_V_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field smds_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__SHIFT                             2
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__WIDTH                             1
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__MASK                    0x00000004U
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__RESET                           0b0
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDS_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field smdc_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__SHIFT                             3
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__WIDTH                             1
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__MASK                    0x00000008U
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__RESET                           0b0
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__MMSL_INT_ENABLE__SMDC_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field fr_count_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__SHIFT                         4
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__WIDTH                         1
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__MASK                0x00000010U
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__RESET                       0b0
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__MMSL_INT_ENABLE__FR_COUNT_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field smd_error_int_en */
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__SHIFT                              5
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__WIDTH                              1
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__MASK                     0x00000020U
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__RESET                            0b0
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_INT_ENABLE__SMD_ERROR_INT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__MMSL_INT_ENABLE__RESERVED_31_6__SHIFT                                 6
#define EMAC_REGS__MMSL_INT_ENABLE__RESERVED_31_6__WIDTH                                26
#define EMAC_REGS__MMSL_INT_ENABLE__RESERVED_31_6__MASK                        0xffffffc0U
#define EMAC_REGS__MMSL_INT_ENABLE__RESERVED_31_6__RESET                                 0
#define EMAC_REGS__MMSL_INT_ENABLE__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__MMSL_INT_ENABLE__TYPE                                          uint32_t
#define EMAC_REGS__MMSL_INT_ENABLE__READ                                       0xffffffc0U
#define EMAC_REGS__MMSL_INT_ENABLE__WRITE                                      0xffffffc0U

#endif /* __MMSL_INT_ENABLE_MACRO__ */


/* macros for mmsl_int_enable */
#define EMAC_REGS__INST_MMSL_INT_ENABLE__NUM                                             1

/* macros for BlueprintGlobalNameSpace::mmsl_int_disable */
#ifndef __EMAC_REGS__MMSL_INT_DISABLE_MACRO__
#define __EMAC_REGS__MMSL_INT_DISABLE_MACRO__

/* macros for field rcv_r_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__SHIFT                          0
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__WIDTH                          1
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__MASK                 0x00000001U
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__RESET                        0b0
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_R_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rcv_v_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__SHIFT                          1
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__WIDTH                          1
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__MASK                 0x00000002U
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__RESET                        0b0
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__MMSL_INT_DISABLE__RCV_V_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field smds_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__SHIFT                           2
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__WIDTH                           1
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__MASK                  0x00000004U
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__RESET                         0b0
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDS_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field smdc_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__SHIFT                           3
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__WIDTH                           1
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__MASK                  0x00000008U
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__RESET                         0b0
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__MMSL_INT_DISABLE__SMDC_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field fr_count_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__SHIFT                       4
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__WIDTH                       1
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__MASK              0x00000010U
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__RESET                     0b0
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__MMSL_INT_DISABLE__FR_COUNT_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field smd_error_int_dis */
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__SHIFT                            5
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__WIDTH                            1
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__MASK                   0x00000020U
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__RESET                          0b0
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_INT_DISABLE__SMD_ERROR_INT_DIS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__MMSL_INT_DISABLE__RESERVED_31_6__SHIFT                                6
#define EMAC_REGS__MMSL_INT_DISABLE__RESERVED_31_6__WIDTH                               26
#define EMAC_REGS__MMSL_INT_DISABLE__RESERVED_31_6__MASK                       0xffffffc0U
#define EMAC_REGS__MMSL_INT_DISABLE__RESERVED_31_6__RESET                                0
#define EMAC_REGS__MMSL_INT_DISABLE__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__MMSL_INT_DISABLE__TYPE                                         uint32_t
#define EMAC_REGS__MMSL_INT_DISABLE__READ                                      0xffffffc0U
#define EMAC_REGS__MMSL_INT_DISABLE__WRITE                                     0xffffffc0U

#endif /* __MMSL_INT_DISABLE_MACRO__ */


/* macros for mmsl_int_disable */
#define EMAC_REGS__INST_MMSL_INT_DISABLE__NUM                                            1

/* macros for BlueprintGlobalNameSpace::mmsl_int_mask */
#ifndef __EMAC_REGS__MMSL_INT_MASK_MACRO__
#define __EMAC_REGS__MMSL_INT_MASK_MACRO__

/* macros for field rcv_r_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__SHIFT                                0
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__WIDTH                                1
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__MASK                       0x00000001U
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__RESET                              0b1
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__MMSL_INT_MASK__RCV_R_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field rcv_v_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__SHIFT                                1
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__WIDTH                                1
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__MASK                       0x00000002U
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__RESET                              0b1
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__MMSL_INT_MASK__RCV_V_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field smds_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__SHIFT                                 2
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__WIDTH                                 1
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__MASK                        0x00000004U
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__RESET                               0b1
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__MMSL_INT_MASK__SMDS_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field smdc_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__SHIFT                                 3
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__WIDTH                                 1
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__MASK                        0x00000008U
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__RESET                               0b1
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__MMSL_INT_MASK__SMDC_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field fr_count_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__SHIFT                             4
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__WIDTH                             1
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__MASK                    0x00000010U
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__RESET                           0b1
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__MMSL_INT_MASK__FR_COUNT_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field smd_error_mask */
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__SHIFT                                  5
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__WIDTH                                  1
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__MASK                         0x00000020U
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__RESET                                0b1
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__MMSL_INT_MASK__SMD_ERROR_MASK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__MMSL_INT_MASK__RESERVED_31_6__SHIFT                                   6
#define EMAC_REGS__MMSL_INT_MASK__RESERVED_31_6__WIDTH                                  26
#define EMAC_REGS__MMSL_INT_MASK__RESERVED_31_6__MASK                          0xffffffc0U
#define EMAC_REGS__MMSL_INT_MASK__RESERVED_31_6__RESET                                   0
#define EMAC_REGS__MMSL_INT_MASK__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__MMSL_INT_MASK__TYPE                                            uint32_t
#define EMAC_REGS__MMSL_INT_MASK__READ                                         0xffffffffU

#endif /* __MMSL_INT_MASK_MACRO__ */


/* macros for mmsl_int_mask */
#define EMAC_REGS__INST_MMSL_INT_MASK__NUM                                               1

/* macros for BlueprintGlobalNameSpace::emac_network_control */
#ifndef __EMAC_REGS__EMAC_NETWORK_CONTROL_MACRO__
#define __EMAC_REGS__EMAC_NETWORK_CONTROL_MACRO__

/* macros for field loopback */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__SHIFT                                 0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__WIDTH                                 1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__MASK                        0x00000001U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__RESET                                 0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field loopback_local */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__SHIFT                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__MASK                  0x00000002U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field enable_receive */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__SHIFT                           2
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__MASK                  0x00000004U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_RECEIVE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(0) << 2)

/* macros for field enable_transmit */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__SHIFT                          3
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__WIDTH                          1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__MASK                 0x00000008U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__RESET                          0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_TRANSMIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field man_port_en */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__SHIFT                              4
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__WIDTH                              1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__MASK                     0x00000010U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__RESET                              0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__MAN_PORT_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field clear_all_stats_regs */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SHIFT                     5
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WIDTH                     1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MASK            0x00000020U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__RESET                     0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field inc_all_stats_regs */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__SHIFT                       6
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__WIDTH                       1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__MASK              0x00000040U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__RESET                       0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__INC_ALL_STATS_REGS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field stats_write_en */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__SHIFT                           7
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__MASK                  0x00000080U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_WRITE_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field back_pressure */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__SHIFT                            8
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__WIDTH                            1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__MASK                   0x00000100U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__RESET                            0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__BACK_PRESSURE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field transmit_start */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__SHIFT                           9
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__MASK                  0x00000200U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_START__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field transmit_halt */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__SHIFT                           10
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__WIDTH                            1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__MASK                   0x00000400U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__RESET                            0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_HALT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(0) << 10)

/* macros for field tx_pause_frame_req */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SHIFT                      11
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WIDTH                       1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MASK              0x00000800U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__RESET                       0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WRITE(src) \
                    (((uint32_t)(src)\
                    << 11) & 0x00000800U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | (((uint32_t)(src) <<\
                    11) & 0x00000800U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 11) & ~0x00000800U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(1) << 11)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000800U) | ((uint32_t)(0) << 11)

/* macros for field tx_pause_frame_zero */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SHIFT                     12
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WIDTH                      1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MASK             0x00001000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__RESET                      0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WRITE(src) \
                    (((uint32_t)(src)\
                    << 12) & 0x00001000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | (((uint32_t)(src) <<\
                    12) & 0x00001000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 12) & ~0x00001000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(1) << 12)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00001000U) | ((uint32_t)(0) << 12)

/* macros for field stats_take_snap */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__SHIFT                         13
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__WIDTH                          1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__MASK                 0x00002000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__RESET                          0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__WRITE(src) \
                    (((uint32_t)(src)\
                    << 13) & 0x00002000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | (((uint32_t)(src) <<\
                    13) & 0x00002000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 13) & ~0x00002000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(1) << 13)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_TAKE_SNAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00002000U) | ((uint32_t)(0) << 13)

/* macros for field stats_read_snap */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__SHIFT                         14
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__WIDTH                          1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__MASK                 0x00004000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__RESET                          0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00004000U) >> 14)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__WRITE(src) \
                    (((uint32_t)(src)\
                    << 14) & 0x00004000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | (((uint32_t)(src) <<\
                    14) & 0x00004000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 14) & ~0x00004000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(1) << 14)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STATS_READ_SNAP__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00004000U) | ((uint32_t)(0) << 14)

/* macros for field store_rx_ts */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__SHIFT                             15
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__WIDTH                              1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__MASK                     0x00008000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__RESET                              0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00008000U) >> 15)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 15) & 0x00008000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | (((uint32_t)(src) <<\
                    15) & 0x00008000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 15) & ~0x00008000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(1) << 15)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_RX_TS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00008000U) | ((uint32_t)(0) << 15)

/* macros for field pfc_enable */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__SHIFT                              16
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__WIDTH                               1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__MASK                      0x00010000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__RESET                               0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00010000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | (((uint32_t)(src) <<\
                    16) & 0x00010000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00010000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field transmit_pfc_priority_based_pause_frame */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SHIFT 17
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WIDTH  1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MASK \
                    0x00020000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__RESET  0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WRITE(src) \
                    (((uint32_t)(src)\
                    << 17) & 0x00020000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | (((uint32_t)(src) <<\
                    17) & 0x00020000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 17) & ~0x00020000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(1) << 17)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00020000U) | ((uint32_t)(0) << 17)

/* macros for field flush_rx_pkt_pclk */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SHIFT                       18
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WIDTH                        1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MASK               0x00040000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__RESET                        0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x00040000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | (((uint32_t)(src) <<\
                    18) & 0x00040000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x00040000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(1) << 18)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00040000U) | ((uint32_t)(0) << 18)

/* macros for field tx_lpi_en */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__SHIFT                               19
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__WIDTH                                1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__MASK                       0x00080000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__RESET                                0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00080000U) >> 19)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 19) & 0x00080000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | (((uint32_t)(src) <<\
                    19) & 0x00080000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 19) & ~0x00080000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(1) << 19)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TX_LPI_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00080000U) | ((uint32_t)(0) << 19)

/* macros for field ptp_unicast_ena */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__SHIFT                         20
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__WIDTH                          1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__MASK                 0x00100000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__RESET                          0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__WRITE(src) \
                    (((uint32_t)(src)\
                    << 20) & 0x00100000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | (((uint32_t)(src) <<\
                    20) & 0x00100000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 20) & ~0x00100000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PTP_UNICAST_ENA__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field alt_sgmii_mode */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__SHIFT                          21
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__MASK                  0x00200000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 21) & 0x00200000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | (((uint32_t)(src) <<\
                    21) & 0x00200000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 21) & ~0x00200000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ALT_SGMII_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field store_udp_offset */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__SHIFT                        22
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__WIDTH                         1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__MASK                0x00400000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__RESET                         0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__WRITE(src) \
                    (((uint32_t)(src)\
                    << 22) & 0x00400000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | (((uint32_t)(src) <<\
                    22) & 0x00400000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 22) & ~0x00400000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__STORE_UDP_OFFSET__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field ext_tsu_port_enable */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SHIFT                     23
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WIDTH                      1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MASK             0x00800000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__RESET                      0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x00800000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | (((uint32_t)(src) <<\
                    23) & 0x00800000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x00800000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field one_step_sync_mode */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SHIFT                      24
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WIDTH                       1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MASK              0x01000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__RESET                       0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 24) & 0x01000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | (((uint32_t)(src) <<\
                    24) & 0x01000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 24) & ~0x01000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ONE_STEP_SYNC_MODE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field pfc_ctrl */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__SHIFT                                25
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__WIDTH                                 1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__MASK                        0x02000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__RESET                                 0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__WRITE(src) \
                    (((uint32_t)(src)\
                    << 25) & 0x02000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | (((uint32_t)(src) <<\
                    25) & 0x02000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 25) & ~0x02000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__PFC_CTRL__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field ext_rxq_sel_en */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__SHIFT                          26
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__WIDTH                           1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__MASK                  0x04000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__RESET                           0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 26) & 0x04000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | (((uint32_t)(src) <<\
                    26) & 0x04000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 26) & ~0x04000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__EXT_RXQ_SEL_EN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field oss_correction_field */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__SHIFT                    27
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__WIDTH                     1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__MASK            0x08000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__RESET                     0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__WRITE(src) \
                    (((uint32_t)(src)\
                    << 27) & 0x08000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | (((uint32_t)(src) <<\
                    27) & 0x08000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 27) & ~0x08000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__OSS_CORRECTION_FIELD__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field sel_mii_on_rgmii */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__SHIFT                        28
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__WIDTH                         1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__MASK                0x10000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__RESET                         0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__READ(src) \
                    (((uint32_t)(src)\
                    & 0x10000000U) >> 28)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x10000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | (((uint32_t)(src) <<\
                    28) & 0x10000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x10000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(1) << 28)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__SEL_MII_ON_RGMII__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x10000000U) | ((uint32_t)(0) << 28)

/* macros for field two_pt_five_gig */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__SHIFT                         29
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__WIDTH                          1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__MASK                 0x20000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__RESET                          0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__READ(src) \
                    (((uint32_t)(src)\
                    & 0x20000000U) >> 29)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__WRITE(src) \
                    (((uint32_t)(src)\
                    << 29) & 0x20000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | (((uint32_t)(src) <<\
                    29) & 0x20000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 29) & ~0x20000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(1) << 29)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TWO_PT_FIVE_GIG__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x20000000U) | ((uint32_t)(0) << 29)

/* macros for field ifg_eats_qav_credit */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SHIFT                     30
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WIDTH                      1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MASK             0x40000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__RESET                      0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field enable_hs_mac */
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__SHIFT                           31
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__WIDTH                            1
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__MASK                   0x80000000U
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__RESET                            0
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__ENABLE_HS_MAC__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__EMAC_NETWORK_CONTROL__TYPE                                     uint32_t
#define EMAC_REGS__EMAC_NETWORK_CONTROL__READ                                  0xfff9c19fU
#define EMAC_REGS__EMAC_NETWORK_CONTROL__WRITE                                 0xfff9c19fU

#endif /* __EMAC_NETWORK_CONTROL_MACRO__ */


/* macros for emac_network_control */
#define EMAC_REGS__INST_EMAC_NETWORK_CONTROL__NUM                                        1

/* macros for emac_network_config */
#define EMAC_REGS__INST_EMAC_NETWORK_CONFIG__NUM                                         1

/* macros for emac_network_status */
#define EMAC_REGS__INST_EMAC_NETWORK_STATUS__NUM                                         1

/* macros for emac_dma_config */
#define EMAC_REGS__INST_EMAC_DMA_CONFIG__NUM                                             1

/* macros for BlueprintGlobalNameSpace::emac_transmit_status */
#ifndef __EMAC_REGS__EMAC_TRANSMIT_STATUS_MACRO__
#define __EMAC_REGS__EMAC_TRANSMIT_STATUS_MACRO__

/* macros for field used_bit_read */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__SHIFT                            0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__WIDTH                            1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__MASK                   0x00000001U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__RESET                            0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__USED_BIT_READ__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field collision_occurred */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__SHIFT                       1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__WIDTH                       1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__MASK              0x00000002U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__RESET                       0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__COLLISION_OCCURRED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field retry_limit_exceeded */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__SHIFT                     2
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WIDTH                     1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MASK            0x00000004U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__RESET                     0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field transmit_go */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__SHIFT                              3
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__WIDTH                              1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__MASK                     0x00000008U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__RESET                              0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_GO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(0) << 3)

/* macros for field amba_error */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__SHIFT                               4
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__WIDTH                               1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__MASK                      0x00000010U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__RESET                               0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__AMBA_ERROR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field transmit_complete */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__SHIFT                        5
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__WIDTH                        1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__MASK               0x00000020U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__RESET                        0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field transmit_under_run */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__SHIFT                       6
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WIDTH                       1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MASK              0x00000040U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__RESET                       0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 6) & 0x00000040U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | (((uint32_t)(src) <<\
                    6) & 0x00000040U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 6) & ~0x00000040U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)

/* macros for field late_collision_occurred */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__SHIFT                  7
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WIDTH                  1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MASK         0x00000080U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__RESET                  0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 7) & 0x00000080U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | (((uint32_t)(src) <<\
                    7) & 0x00000080U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 7) & ~0x00000080U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)

/* macros for field resp_not_ok */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__SHIFT                              8
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__WIDTH                              1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__MASK                     0x00000100U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__RESET                              0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 8) & 0x00000100U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | (((uint32_t)(src) <<\
                    8) & 0x00000100U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 8) & ~0x00000100U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)

/* macros for field tx_mac_lockup_detected */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__SHIFT                   9
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__WIDTH                   1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__MASK          0x00000200U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__RESET                   0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 9) & 0x00000200U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | (((uint32_t)(src) <<\
                    9) & 0x00000200U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 9) & ~0x00000200U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_MAC_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)

/* macros for field tx_dma_lockup_detected */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__SHIFT                  10
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__WIDTH                   1
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__MASK          0x00000400U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__RESET                   0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000400U) >> 10)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 10) & 0x00000400U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | (((uint32_t)(src) <<\
                    10) & 0x00000400U)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 10) & ~0x00000400U)))
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TX_DMA_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000400U) | ((uint32_t)(1) << 10)

/* macros for field reserved_31_11 */
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESERVED_31_11__SHIFT                          11
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESERVED_31_11__WIDTH                          21
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESERVED_31_11__MASK                  0xfffff800U
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESERVED_31_11__RESET                           0
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__RESERVED_31_11__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffff800U) >> 11)
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__TYPE                                     uint32_t
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__READ                                  0xffffffffU
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__WRITE                                 0xffffffffU
#define EMAC_REGS__EMAC_TRANSMIT_STATUS__WOCLR                                 0x000007f7U

#endif /* __EMAC_TRANSMIT_STATUS_MACRO__ */


/* macros for emac_transmit_status */
#define EMAC_REGS__INST_EMAC_TRANSMIT_STATUS__NUM                                        1

/* macros for emac_receive_q_ptr */
#define EMAC_REGS__INST_EMAC_RECEIVE_Q_PTR__NUM                                          1

/* macros for emac_transmit_q_ptr */
#define EMAC_REGS__INST_EMAC_TRANSMIT_Q_PTR__NUM                                         1

/* macros for BlueprintGlobalNameSpace::emac_receive_status */
#ifndef __EMAC_REGS__EMAC_RECEIVE_STATUS_MACRO__
#define __EMAC_REGS__EMAC_RECEIVE_STATUS_MACRO__

/* macros for field buffer_not_available */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__SHIFT                      0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WIDTH                      1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MASK             0x00000001U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__RESET                      0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)

/* macros for field frame_received */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__SHIFT                            1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__WIDTH                            1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__MASK                   0x00000002U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__RESET                            0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 1) & 0x00000002U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | (((uint32_t)(src) <<\
                    1) & 0x00000002U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 1) & ~0x00000002U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__FRAME_RECEIVED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)

/* macros for field receive_overrun */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__SHIFT                           2
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__WIDTH                           1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__MASK                  0x00000004U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__RESET                           0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000004U) >> 2)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__WRITE(src) \
                    (((uint32_t)(src)\
                    << 2) & 0x00000004U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | (((uint32_t)(src) <<\
                    2) & 0x00000004U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 2) & ~0x00000004U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RECEIVE_OVERRUN__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000004U) | ((uint32_t)(1) << 2)

/* macros for field resp_not_ok */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__SHIFT                               3
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__WIDTH                               1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__MASK                      0x00000008U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__RESET                               0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000008U) >> 3)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 3) & 0x00000008U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | (((uint32_t)(src) <<\
                    3) & 0x00000008U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 3) & ~0x00000008U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESP_NOT_OK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000008U) | ((uint32_t)(1) << 3)

/* macros for field rx_mac_lockup_detected */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__SHIFT                    4
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__WIDTH                    1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__MASK           0x00000010U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__RESET                    0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x00000010U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | (((uint32_t)(src) <<\
                    4) & 0x00000010U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x00000010U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_MAC_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)

/* macros for field rx_dma_lockup_detected */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__SHIFT                    5
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__WIDTH                    1
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__MASK           0x00000020U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__RESET                    0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__WRITE(src) \
                    (((uint32_t)(src)\
                    << 5) & 0x00000020U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | (((uint32_t)(src) <<\
                    5) & 0x00000020U)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 5) & ~0x00000020U)))
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RX_DMA_LOCKUP_DETECTED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)

/* macros for field reserved_31_6 */
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESERVED_31_6__SHIFT                             6
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESERVED_31_6__WIDTH                            26
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESERVED_31_6__MASK                    0xffffffc0U
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESERVED_31_6__RESET                             0
#define EMAC_REGS__EMAC_RECEIVE_STATUS__RESERVED_31_6__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffffc0U) >> 6)
#define EMAC_REGS__EMAC_RECEIVE_STATUS__TYPE                                      uint32_t
#define EMAC_REGS__EMAC_RECEIVE_STATUS__READ                                   0xffffffffU
#define EMAC_REGS__EMAC_RECEIVE_STATUS__WRITE                                  0xffffffffU
#define EMAC_REGS__EMAC_RECEIVE_STATUS__WOCLR                                  0x0000003fU

#endif /* __EMAC_RECEIVE_STATUS_MACRO__ */


/* macros for emac_receive_status */
#define EMAC_REGS__INST_EMAC_RECEIVE_STATUS__NUM                                         1

/* macros for emac_int_status */
#define EMAC_REGS__INST_EMAC_INT_STATUS__NUM                                             1

/* macros for emac_int_enable */
#define EMAC_REGS__INST_EMAC_INT_ENABLE__NUM                                             1

/* macros for emac_int_disable */
#define EMAC_REGS__INST_EMAC_INT_DISABLE__NUM                                            1

/* macros for emac_int_mask */
#define EMAC_REGS__INST_EMAC_INT_MASK__NUM                                               1

/* macros for BlueprintGlobalNameSpace::emac_phy_management */
#ifndef __EMAC_REGS__EMAC_PHY_MANAGEMENT_MACRO__
#define __EMAC_REGS__EMAC_PHY_MANAGEMENT_MACRO__

/* macros for field phy_write_read_data */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__SHIFT                       0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WIDTH                      16
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MASK              0x0000ffffU
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__RESET                       0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000ffffU) | ((uint32_t)(src) &\
                    0x0000ffffU)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_WRITE_READ_DATA__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000ffffU)))

/* macros for field write10 */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__SHIFT                                  16
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__WIDTH                                   2
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__MASK                          0x00030000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__RESET                                   0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00030000U) >> 16)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__WRITE(src) \
                    (((uint32_t)(src)\
                    << 16) & 0x00030000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00030000U) | (((uint32_t)(src) <<\
                    16) & 0x00030000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE10__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 16) & ~0x00030000U)))

/* macros for field register_address */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__SHIFT                         18
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__WIDTH                          5
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__MASK                 0x007c0000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__RESET                          0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x007c0000U) >> 18)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 18) & 0x007c0000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x007c0000U) | (((uint32_t)(src) <<\
                    18) & 0x007c0000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__REGISTER_ADDRESS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 18) & ~0x007c0000U)))

/* macros for field phy_address */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__SHIFT                              23
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__WIDTH                               5
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__MASK                      0x0f800000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__RESET                               0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0f800000U) >> 23)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 23) & 0x0f800000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0f800000U) | (((uint32_t)(src) <<\
                    23) & 0x0f800000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__PHY_ADDRESS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 23) & ~0x0f800000U)))

/* macros for field operation */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__SHIFT                                28
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__WIDTH                                 2
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__MASK                        0x30000000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__RESET                                 0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__READ(src) \
                    (((uint32_t)(src)\
                    & 0x30000000U) >> 28)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__WRITE(src) \
                    (((uint32_t)(src)\
                    << 28) & 0x30000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x30000000U) | (((uint32_t)(src) <<\
                    28) & 0x30000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__OPERATION__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 28) & ~0x30000000U)))

/* macros for field write1 */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__SHIFT                                   30
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__WIDTH                                    1
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__MASK                           0x40000000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__RESET                                    0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0x40000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | (((uint32_t)(src) <<\
                    30) & 0x40000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0x40000000U)))
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE1__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field write0 */
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__SHIFT                                   31
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__WIDTH                                    1
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__MASK                           0x80000000U
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__RESET                                    0
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__TYPE                                      uint32_t
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__READ                                   0xffffffffU
#define EMAC_REGS__EMAC_PHY_MANAGEMENT__WRITE                                  0xffffffffU

#endif /* __EMAC_PHY_MANAGEMENT_MACRO__ */


/* macros for emac_phy_management */
#define EMAC_REGS__INST_EMAC_PHY_MANAGEMENT__NUM                                         1

/* macros for emac_pause_time */
#define EMAC_REGS__INST_EMAC_PAUSE_TIME__NUM                                             1

/* macros for emac_tx_pause_quantum */
#define EMAC_REGS__INST_EMAC_TX_PAUSE_QUANTUM__NUM                                       1

/* macros for BlueprintGlobalNameSpace::emac_pbuf_txcutthru */
#ifndef __EMAC_REGS__EMAC_PBUF_TXCUTTHRU_MACRO__
#define __EMAC_REGS__EMAC_PBUF_TXCUTTHRU_MACRO__

/* macros for field dma_tx_cutthru_threshold */
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__SHIFT                  0
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WIDTH                 11
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MASK         0x000007ffU
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__RESET               2047
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((uint32_t)(src) &\
                    0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field reserved */
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__RESERVED__SHIFT                                 11
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__RESERVED__WIDTH                                 20
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__RESERVED__MASK                         0x7ffff800U
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__RESERVED__RESET                                  0
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__RESERVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7ffff800U) >> 11)

/* macros for field dma_tx_cutthru */
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SHIFT                           31
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WIDTH                            1
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MASK                   0x80000000U
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__RESET                            0
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__TYPE                                      uint32_t
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__READ                                   0xffffffffU
#define EMAC_REGS__EMAC_PBUF_TXCUTTHRU__WRITE                                  0xffffffffU

#endif /* __EMAC_PBUF_TXCUTTHRU_MACRO__ */


/* macros for emac_pbuf_txcutthru */
#define EMAC_REGS__INST_EMAC_PBUF_TXCUTTHRU__NUM                                         1

/* macros for BlueprintGlobalNameSpace::emac_pbuf_rxcutthru */
#ifndef __EMAC_REGS__EMAC_PBUF_RXCUTTHRU_MACRO__
#define __EMAC_REGS__EMAC_PBUF_RXCUTTHRU_MACRO__

/* macros for field dma_rx_cutthru_threshold */
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__SHIFT                  0
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WIDTH                 11
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MASK         0x000007ffU
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__RESET               2047
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000007ffU) | ((uint32_t)(src) &\
                    0x000007ffU)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000007ffU)))

/* macros for field reserved */
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__RESERVED__SHIFT                                 11
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__RESERVED__WIDTH                                 20
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__RESERVED__MASK                         0x7ffff800U
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__RESERVED__RESET                                  0
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__RESERVED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x7ffff800U) >> 11)

/* macros for field dma_rx_cutthru */
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SHIFT                           31
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WIDTH                            1
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MASK                   0x80000000U
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__RESET                            0
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WRITE(src) \
                    (((uint32_t)(src)\
                    << 31) & 0x80000000U)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | (((uint32_t)(src) <<\
                    31) & 0x80000000U)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 31) & ~0x80000000U)))
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__TYPE                                      uint32_t
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__READ                                   0xffffffffU
#define EMAC_REGS__EMAC_PBUF_RXCUTTHRU__WRITE                                  0xffffffffU

#endif /* __EMAC_PBUF_RXCUTTHRU_MACRO__ */


/* macros for emac_pbuf_rxcutthru */
#define EMAC_REGS__INST_EMAC_PBUF_RXCUTTHRU__NUM                                         1

/* macros for emac_jumbo_max_length */
#define EMAC_REGS__INST_EMAC_JUMBO_MAX_LENGTH__NUM                                       1

/* macros for emac_external_fifo_interface */
#define EMAC_REGS__INST_EMAC_EXTERNAL_FIFO_INTERFACE__NUM                                1

/* macros for emac_hs_mac_config */
#define EMAC_REGS__INST_EMAC_HS_MAC_CONFIG__NUM                                          1

/* macros for emac_axi_max_pipeline */
#define EMAC_REGS__INST_EMAC_AXI_MAX_PIPELINE__NUM                                       1

/* macros for emac_int_moderation */
#define EMAC_REGS__INST_EMAC_INT_MODERATION__NUM                                         1

/* macros for emac_sys_wake_time */
#define EMAC_REGS__INST_EMAC_SYS_WAKE_TIME__NUM                                          1

/* macros for emac_lockup_config */
#define EMAC_REGS__INST_EMAC_LOCKUP_CONFIG__NUM                                          1

/* macros for emac_mac_lockup_time */
#define EMAC_REGS__INST_EMAC_MAC_LOCKUP_TIME__NUM                                        1

/* macros for BlueprintGlobalNameSpace::emac_lockup_config3 */
#ifndef __EMAC_REGS__EMAC_LOCKUP_CONFIG3_MACRO__
#define __EMAC_REGS__EMAC_LOCKUP_CONFIG3_MACRO__

/* macros for field dma_tx_lockup_en_q_0 */
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__SHIFT                      0
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__WIDTH                      1
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__MASK             0x00000001U
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__RESET                      0
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__DMA_TX_LOCKUP_EN_Q_0__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_31_1 */
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__RESERVED_31_1__SHIFT                             1
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__RESERVED_31_1__WIDTH                            31
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__RESERVED_31_1__MASK                    0xfffffffeU
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__RESERVED_31_1__RESET                             0
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__RESERVED_31_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffeU) >> 1)
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__TYPE                                      uint32_t
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__READ                                   0xffffffffU
#define EMAC_REGS__EMAC_LOCKUP_CONFIG3__WRITE                                  0xffffffffU

#endif /* __EMAC_LOCKUP_CONFIG3_MACRO__ */


/* macros for emac_lockup_config3 */
#define EMAC_REGS__INST_EMAC_LOCKUP_CONFIG3__NUM                                         1

/* macros for emac_rx_water_mark */
#define EMAC_REGS__INST_EMAC_RX_WATER_MARK__NUM                                          1

/* macros for emac_hash_bottom */
#define EMAC_REGS__INST_EMAC_HASH_BOTTOM__NUM                                            1

/* macros for emac_hash_top */
#define EMAC_REGS__INST_EMAC_HASH_TOP__NUM                                               1

/* macros for emac_spec_add1_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD1_BOTTOM__NUM                                       1

/* macros for emac_spec_add1_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD1_TOP__NUM                                          1

/* macros for emac_spec_add2_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD2_BOTTOM__NUM                                       1

/* macros for emac_spec_add2_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD2_TOP__NUM                                          1

/* macros for emac_spec_add3_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD3_BOTTOM__NUM                                       1

/* macros for emac_spec_add3_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD3_TOP__NUM                                          1

/* macros for emac_spec_add4_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD4_BOTTOM__NUM                                       1

/* macros for emac_spec_add4_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD4_TOP__NUM                                          1

/* macros for emac_spec_type1 */
#define EMAC_REGS__INST_EMAC_SPEC_TYPE1__NUM                                             1

/* macros for emac_spec_type2 */
#define EMAC_REGS__INST_EMAC_SPEC_TYPE2__NUM                                             1

/* macros for emac_spec_type3 */
#define EMAC_REGS__INST_EMAC_SPEC_TYPE3__NUM                                             1

/* macros for emac_spec_type4 */
#define EMAC_REGS__INST_EMAC_SPEC_TYPE4__NUM                                             1

/* macros for emac_wol_register */
#define EMAC_REGS__INST_EMAC_WOL_REGISTER__NUM                                           1

/* macros for emac_stretch_ratio */
#define EMAC_REGS__INST_EMAC_STRETCH_RATIO__NUM                                          1

/* macros for emac_stacked_vlan */
#define EMAC_REGS__INST_EMAC_STACKED_VLAN__NUM                                           1

/* macros for emac_tx_pfc_pause */
#define EMAC_REGS__INST_EMAC_TX_PFC_PAUSE__NUM                                           1

/* macros for emac_mask_add1_bottom */
#define EMAC_REGS__INST_EMAC_MASK_ADD1_BOTTOM__NUM                                       1

/* macros for emac_mask_add1_top */
#define EMAC_REGS__INST_EMAC_MASK_ADD1_TOP__NUM                                          1

/* macros for emac_dma_addr_or_mask */
#define EMAC_REGS__INST_EMAC_DMA_ADDR_OR_MASK__NUM                                       1

/* macros for emac_rx_ptp_unicast */
#define EMAC_REGS__INST_EMAC_RX_PTP_UNICAST__NUM                                         1

/* macros for emac_tx_ptp_unicast */
#define EMAC_REGS__INST_EMAC_TX_PTP_UNICAST__NUM                                         1

/* macros for emac_tsu_nsec_cmp */
#define EMAC_REGS__INST_EMAC_TSU_NSEC_CMP__NUM                                           1

/* macros for emac_tsu_sec_cmp */
#define EMAC_REGS__INST_EMAC_TSU_SEC_CMP__NUM                                            1

/* macros for emac_tsu_msb_sec_cmp */
#define EMAC_REGS__INST_EMAC_TSU_MSB_SEC_CMP__NUM                                        1

/* macros for emac_tsu_ptp_tx_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_TX_MSB_SEC__NUM                                     1

/* macros for emac_tsu_ptp_rx_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_RX_MSB_SEC__NUM                                     1

/* macros for emac_tsu_peer_tx_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_TX_MSB_SEC__NUM                                    1

/* macros for emac_tsu_peer_rx_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_RX_MSB_SEC__NUM                                    1

/* macros for emac_dpram_fill_dbg */
#define EMAC_REGS__INST_EMAC_DPRAM_FILL_DBG__NUM                                         1

/* macros for emac_revision_reg */
#define EMAC_REGS__INST_EMAC_REVISION_REG__NUM                                           1

/* macros for emac_octets_txed_bottom */
#define EMAC_REGS__INST_EMAC_OCTETS_TXED_BOTTOM__NUM                                     1

/* macros for emac_octets_txed_top */
#define EMAC_REGS__INST_EMAC_OCTETS_TXED_TOP__NUM                                        1

/* macros for emac_frames_txed_ok */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_OK__NUM                                         1

/* macros for emac_broadcast_txed */
#define EMAC_REGS__INST_EMAC_BROADCAST_TXED__NUM                                         1

/* macros for emac_multicast_txed */
#define EMAC_REGS__INST_EMAC_MULTICAST_TXED__NUM                                         1

/* macros for emac_pause_frames_txed */
#define EMAC_REGS__INST_EMAC_PAUSE_FRAMES_TXED__NUM                                      1

/* macros for emac_frames_txed_64 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_64__NUM                                         1

/* macros for emac_frames_txed_65 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_65__NUM                                         1

/* macros for emac_frames_txed_128 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_128__NUM                                        1

/* macros for emac_frames_txed_256 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_256__NUM                                        1

/* macros for emac_frames_txed_512 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_512__NUM                                        1

/* macros for emac_frames_txed_1024 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_1024__NUM                                       1

/* macros for emac_frames_txed_1519 */
#define EMAC_REGS__INST_EMAC_FRAMES_TXED_1519__NUM                                       1

/* macros for emac_tx_underruns */
#define EMAC_REGS__INST_EMAC_TX_UNDERRUNS__NUM                                           1

/* macros for emac_single_collisions */
#define EMAC_REGS__INST_EMAC_SINGLE_COLLISIONS__NUM                                      1

/* macros for emac_multiple_collisions */
#define EMAC_REGS__INST_EMAC_MULTIPLE_COLLISIONS__NUM                                    1

/* macros for emac_excessive_collisions */
#define EMAC_REGS__INST_EMAC_EXCESSIVE_COLLISIONS__NUM                                   1

/* macros for emac_late_collisions */
#define EMAC_REGS__INST_EMAC_LATE_COLLISIONS__NUM                                        1

/* macros for emac_deferred_frames */
#define EMAC_REGS__INST_EMAC_DEFERRED_FRAMES__NUM                                        1

/* macros for emac_crs_errors */
#define EMAC_REGS__INST_EMAC_CRS_ERRORS__NUM                                             1

/* macros for emac_octets_rxed_bottom */
#define EMAC_REGS__INST_EMAC_OCTETS_RXED_BOTTOM__NUM                                     1

/* macros for emac_octets_rxed_top */
#define EMAC_REGS__INST_EMAC_OCTETS_RXED_TOP__NUM                                        1

/* macros for emac_frames_rxed_ok */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_OK__NUM                                         1

/* macros for emac_broadcast_rxed */
#define EMAC_REGS__INST_EMAC_BROADCAST_RXED__NUM                                         1

/* macros for emac_multicast_rxed */
#define EMAC_REGS__INST_EMAC_MULTICAST_RXED__NUM                                         1

/* macros for emac_pause_frames_rxed */
#define EMAC_REGS__INST_EMAC_PAUSE_FRAMES_RXED__NUM                                      1

/* macros for emac_frames_rxed_64 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_64__NUM                                         1

/* macros for emac_frames_rxed_65 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_65__NUM                                         1

/* macros for emac_frames_rxed_128 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_128__NUM                                        1

/* macros for emac_frames_rxed_256 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_256__NUM                                        1

/* macros for emac_frames_rxed_512 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_512__NUM                                        1

/* macros for emac_frames_rxed_1024 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_1024__NUM                                       1

/* macros for emac_frames_rxed_1519 */
#define EMAC_REGS__INST_EMAC_FRAMES_RXED_1519__NUM                                       1

/* macros for emac_undersize_frames */
#define EMAC_REGS__INST_EMAC_UNDERSIZE_FRAMES__NUM                                       1

/* macros for emac_excessive_rx_length */
#define EMAC_REGS__INST_EMAC_EXCESSIVE_RX_LENGTH__NUM                                    1

/* macros for emac_rx_jabbers */
#define EMAC_REGS__INST_EMAC_RX_JABBERS__NUM                                             1

/* macros for emac_fcs_errors */
#define EMAC_REGS__INST_EMAC_FCS_ERRORS__NUM                                             1

/* macros for emac_rx_length_errors */
#define EMAC_REGS__INST_EMAC_RX_LENGTH_ERRORS__NUM                                       1

/* macros for emac_rx_symbol_errors */
#define EMAC_REGS__INST_EMAC_RX_SYMBOL_ERRORS__NUM                                       1

/* macros for emac_alignment_errors */
#define EMAC_REGS__INST_EMAC_ALIGNMENT_ERRORS__NUM                                       1

/* macros for emac_rx_resource_errors */
#define EMAC_REGS__INST_EMAC_RX_RESOURCE_ERRORS__NUM                                     1

/* macros for emac_rx_overruns */
#define EMAC_REGS__INST_EMAC_RX_OVERRUNS__NUM                                            1

/* macros for emac_rx_ip_ck_errors */
#define EMAC_REGS__INST_EMAC_RX_IP_CK_ERRORS__NUM                                        1

/* macros for emac_rx_tcp_ck_errors */
#define EMAC_REGS__INST_EMAC_RX_TCP_CK_ERRORS__NUM                                       1

/* macros for emac_rx_udp_ck_errors */
#define EMAC_REGS__INST_EMAC_RX_UDP_CK_ERRORS__NUM                                       1

/* macros for emac_auto_flushed_pkts */
#define EMAC_REGS__INST_EMAC_AUTO_FLUSHED_PKTS__NUM                                      1

/* macros for emac_tsu_timer_incr_sub_nsec */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_INCR_SUB_NSEC__NUM                                1

/* macros for emac_tsu_timer_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_MSB_SEC__NUM                                      1

/* macros for emac_tsu_strobe_msb_sec */
#define EMAC_REGS__INST_EMAC_TSU_STROBE_MSB_SEC__NUM                                     1

/* macros for emac_tsu_strobe_sec */
#define EMAC_REGS__INST_EMAC_TSU_STROBE_SEC__NUM                                         1

/* macros for emac_tsu_strobe_nsec */
#define EMAC_REGS__INST_EMAC_TSU_STROBE_NSEC__NUM                                        1

/* macros for emac_tsu_timer_sec */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_SEC__NUM                                          1

/* macros for emac_tsu_timer_nsec */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_NSEC__NUM                                         1

/* macros for emac_tsu_timer_adjust */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_ADJUST__NUM                                       1

/* macros for emac_tsu_timer_incr */
#define EMAC_REGS__INST_EMAC_TSU_TIMER_INCR__NUM                                         1

/* macros for emac_tsu_ptp_tx_sec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_TX_SEC__NUM                                         1

/* macros for emac_tsu_ptp_tx_nsec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_TX_NSEC__NUM                                        1

/* macros for emac_tsu_ptp_rx_sec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_RX_SEC__NUM                                         1

/* macros for emac_tsu_ptp_rx_nsec */
#define EMAC_REGS__INST_EMAC_TSU_PTP_RX_NSEC__NUM                                        1

/* macros for emac_tsu_peer_tx_sec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_TX_SEC__NUM                                        1

/* macros for emac_tsu_peer_tx_nsec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_TX_NSEC__NUM                                       1

/* macros for emac_tsu_peer_rx_sec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_RX_SEC__NUM                                        1

/* macros for emac_tsu_peer_rx_nsec */
#define EMAC_REGS__INST_EMAC_TSU_PEER_RX_NSEC__NUM                                       1

/* macros for emac_tx_pause_quantum1 */
#define EMAC_REGS__INST_EMAC_TX_PAUSE_QUANTUM1__NUM                                      1

/* macros for emac_tx_pause_quantum2 */
#define EMAC_REGS__INST_EMAC_TX_PAUSE_QUANTUM2__NUM                                      1

/* macros for emac_tx_pause_quantum3 */
#define EMAC_REGS__INST_EMAC_TX_PAUSE_QUANTUM3__NUM                                      1

/* macros for emac_pfc_status */
#define EMAC_REGS__INST_EMAC_PFC_STATUS__NUM                                             1

/* macros for emac_rx_lpi */
#define EMAC_REGS__INST_EMAC_RX_LPI__NUM                                                 1

/* macros for emac_rx_lpi_time */
#define EMAC_REGS__INST_EMAC_RX_LPI_TIME__NUM                                            1

/* macros for emac_tx_lpi */
#define EMAC_REGS__INST_EMAC_TX_LPI__NUM                                                 1

/* macros for emac_tx_lpi_time */
#define EMAC_REGS__INST_EMAC_TX_LPI_TIME__NUM                                            1

/* macros for BlueprintGlobalNameSpace::emac_designcfg_debug1 */
#ifndef __EMAC_REGS__EMAC_DESIGNCFG_DEBUG1_MACRO__
#define __EMAC_REGS__EMAC_DESIGNCFG_DEBUG1_MACRO__

/* macros for field no_pcs */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__SHIFT                                  0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__WIDTH                                  1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__MASK                         0x00000001U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__RESET                                  0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_PCS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field exclude_qbv */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__SHIFT                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__MASK                    0x00000002U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__RESET                             0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000002U) >> 1)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(1) << 1)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_QBV__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000002U) | ((uint32_t)(0) << 1)

/* macros for field reserved_3_2 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_3_2__SHIFT                            2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_3_2__WIDTH                            2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_3_2__MASK                   0x0000000cU
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_3_2__RESET                            0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_3_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000000cU) >> 2)

/* macros for field int_loopback */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__SHIFT                            4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__WIDTH                            1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__MASK                   0x00000010U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__RESET                            1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000010U) >> 4)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(1) << 4)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__INT_LOOPBACK__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000010U) | ((uint32_t)(0) << 4)

/* macros for field reserved_5 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__SHIFT                              5
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__WIDTH                              1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__MASK                     0x00000020U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__RESET                              0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000020U) >> 5)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(1) << 5)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_5__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000020U) | ((uint32_t)(0) << 5)

/* macros for field ext_fifo_interface */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SHIFT                      6
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__WIDTH                      1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__MASK             0x00000040U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__RESET                      0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000040U) >> 6)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(1) << 6)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000040U) | ((uint32_t)(0) << 6)

/* macros for field reserved_7 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__SHIFT                              7
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__WIDTH                              1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__MASK                     0x00000080U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__RESET                              0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000080U) >> 7)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(1) << 7)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_7__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000080U) | ((uint32_t)(0) << 7)

/* macros for field reserved_8 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__SHIFT                              8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__WIDTH                              1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__MASK                     0x00000100U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__RESET                              1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000100U) >> 8)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(1) << 8)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_8__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000100U) | ((uint32_t)(0) << 8)

/* macros for field user_io */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__SHIFT                                 9
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__WIDTH                                 1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__MASK                        0x00000200U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__RESET                                 0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00000200U) >> 9)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(1) << 9)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000200U) | ((uint32_t)(0) << 9)

/* macros for field user_out_width */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_OUT_WIDTH__SHIFT                         10
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_OUT_WIDTH__WIDTH                          5
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_OUT_WIDTH__MASK                 0x00007c00U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_OUT_WIDTH__RESET                          1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_OUT_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00007c00U) >> 10)

/* macros for field user_in_width */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IN_WIDTH__SHIFT                          15
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IN_WIDTH__WIDTH                           5
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IN_WIDTH__MASK                  0x000f8000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IN_WIDTH__RESET                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__USER_IN_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f8000U) >> 15)

/* macros for field reserved_20 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__SHIFT                            20
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__MASK                    0x00100000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__RESET                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__RESERVED_20__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field no_stats */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__SHIFT                               21
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__WIDTH                                1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__MASK                       0x00200000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__RESET                                0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_STATS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field no_snapshot */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__SHIFT                            22
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__MASK                    0x00400000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__RESET                             0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__NO_SNAPSHOT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field irq_read_clear */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SHIFT                         23
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__WIDTH                          1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__MASK                 0x00800000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__RESET                          1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field exclude_cbs */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__SHIFT                            24
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__MASK                    0x01000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__RESET                             0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__EXCLUDE_CBS__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field dma_bus_width */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__SHIFT                          25
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__WIDTH                           3
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__MASK                  0x0e000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__RESET                           2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0e000000U) >> 25)

/* macros for field axi_cache_value */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__SHIFT                        28
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__WIDTH                         4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__MASK                0xf0000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__RESET                         0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__TYPE                                    uint32_t
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG1__READ                                 0xffffffffU

#endif /* __EMAC_DESIGNCFG_DEBUG1_MACRO__ */


/* macros for emac_designcfg_debug1 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG1__NUM                                       1

/* macros for BlueprintGlobalNameSpace::emac_designcfg_debug2 */
#ifndef __EMAC_REGS__EMAC_DESIGNCFG_DEBUG2_MACRO__
#define __EMAC_REGS__EMAC_DESIGNCFG_DEBUG2_MACRO__

/* macros for field jumbo_max_length */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__SHIFT                        0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__WIDTH                       14
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__MASK               0x00003fffU
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__RESET                    10240
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00003fffU)

/* macros for field reserved_15_14 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RESERVED_15_14__SHIFT                         14
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RESERVED_15_14__WIDTH                          2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RESERVED_15_14__MASK                 0x0000c000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RESERVED_15_14__RESET                          0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RESERVED_15_14__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000c000U) >> 14)

/* macros for field hprot_value */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__HPROT_VALUE__SHIFT                            16
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__HPROT_VALUE__WIDTH                             4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__HPROT_VALUE__MASK                    0x000f0000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__HPROT_VALUE__RESET                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__HPROT_VALUE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field rx_pkt_buffer */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SHIFT                          20
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__WIDTH                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__MASK                  0x00100000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__RESET                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PKT_BUFFER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field tx_pkt_buffer */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SHIFT                          21
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__WIDTH                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__MASK                  0x00200000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__RESET                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PKT_BUFFER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field rx_pbuf_addr */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PBUF_ADDR__SHIFT                           22
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PBUF_ADDR__WIDTH                            4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PBUF_ADDR__MASK                   0x03c00000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PBUF_ADDR__RESET                           11
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__RX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x03c00000U) >> 22)

/* macros for field tx_pbuf_addr */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PBUF_ADDR__SHIFT                           26
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PBUF_ADDR__WIDTH                            4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PBUF_ADDR__MASK                   0x3c000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PBUF_ADDR__RESET                           11
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x3c000000U) >> 26)

/* macros for field axi */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__SHIFT                                    30
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__WIDTH                                     1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__MASK                            0x40000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__RESET                                     1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__READ(src) \
                    (((uint32_t)(src)\
                    & 0x40000000U) >> 30)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(1) << 30)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__AXI__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x40000000U) | ((uint32_t)(0) << 30)

/* macros for field spram */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__SHIFT                                  31
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__WIDTH                                   1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__MASK                          0x80000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__RESET                                   0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x80000000U) >> 31)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(1) << 31)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__SPRAM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x80000000U) | ((uint32_t)(0) << 31)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__TYPE                                    uint32_t
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG2__READ                                 0xffffffffU

#endif /* __EMAC_DESIGNCFG_DEBUG2_MACRO__ */


/* macros for emac_designcfg_debug2 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG2__NUM                                       1

/* macros for emac_designcfg_debug3 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG3__NUM                                       1

/* macros for emac_designcfg_debug4 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG4__NUM                                       1

/* macros for emac_designcfg_debug5 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG5__NUM                                       1

/* macros for BlueprintGlobalNameSpace::emac_designcfg_debug6 */
#ifndef __EMAC_REGS__EMAC_DESIGNCFG_DEBUG6_MACRO__
#define __EMAC_REGS__EMAC_DESIGNCFG_DEBUG6_MACRO__

/* macros for field reserved_15_0 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_15_0__SHIFT                           0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_15_0__WIDTH                          16
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_15_0__MASK                  0x0000ffffU
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_15_0__RESET                           0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_15_0__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000ffffU)

/* macros for field tx_pbuf_queue_segment_size */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__SHIFT             16
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__WIDTH              4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__MASK     0x000f0000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__RESET              4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000f0000U) >> 16)

/* macros for field ext_tsu_timer */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SHIFT                          20
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__WIDTH                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__MASK                  0x00100000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__RESET                           1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00100000U) >> 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(1) << 20)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__EXT_TSU_TIMER__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00100000U) | ((uint32_t)(0) << 20)

/* macros for field tx_add_fifo_if */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SHIFT                         21
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__WIDTH                          1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__MASK                 0x00200000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__RESET                          0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00200000U) >> 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(1) << 21)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00200000U) | ((uint32_t)(0) << 21)

/* macros for field host_if_soft_select */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SHIFT                    22
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__WIDTH                     1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__MASK            0x00400000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__RESET                     1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00400000U) >> 22)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(1) << 22)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00400000U) | ((uint32_t)(0) << 22)

/* macros for field dma_addr_width_is_64b */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SHIFT                  23
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__WIDTH                   1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__MASK          0x00800000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__RESET                   1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00800000U) >> 23)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(1) << 23)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00800000U) | ((uint32_t)(0) << 23)

/* macros for field pfc_multi_quantum */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SHIFT                      24
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__WIDTH                       1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__MASK              0x01000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__RESET                       1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01000000U) >> 24)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(1) << 24)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x01000000U) | ((uint32_t)(0) << 24)

/* macros for field pbuf_cutthru */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SHIFT                           25
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__WIDTH                            1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__MASK                   0x02000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__RESET                            1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_CUTTHRU__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field reserved_26 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__SHIFT                            26
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__MASK                    0x04000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__RESET                             0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_26__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field pbuf_lso */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__SHIFT                               27
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__WIDTH                                1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__MASK                       0x08000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__RESET                                0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__PBUF_LSO__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field reserved_31_28 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_31_28__SHIFT                         28
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_31_28__WIDTH                          4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_31_28__MASK                 0xf0000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_31_28__RESET                          0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__RESERVED_31_28__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__TYPE                                    uint32_t
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG6__READ                                 0xffffffffU

#endif /* __EMAC_DESIGNCFG_DEBUG6_MACRO__ */


/* macros for emac_designcfg_debug6 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG6__NUM                                       1

/* macros for emac_designcfg_debug7 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG7__NUM                                       1

/* macros for BlueprintGlobalNameSpace::emac_designcfg_debug8 */
#ifndef __EMAC_REGS__EMAC_DESIGNCFG_DEBUG8_MACRO__
#define __EMAC_REGS__EMAC_DESIGNCFG_DEBUG8_MACRO__

/* macros for field num_scr2_compare_regs */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__SHIFT                   0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__WIDTH                   8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__MASK          0x000000ffU
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__RESET                   6
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field num_scr2_ethtype_regs */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__SHIFT                   8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__WIDTH                   8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__MASK          0x0000ff00U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__RESET                   0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field num_type2_screeners */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__SHIFT                    16
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__WIDTH                     8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__MASK            0x00ff0000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__RESET                     2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00ff0000U) >> 16)

/* macros for field num_type1_screeners */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__SHIFT                    24
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__WIDTH                     8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__MASK            0xff000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__RESET                     1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__READ(src) \
                    (((uint32_t)(src)\
                    & 0xff000000U) >> 24)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__TYPE                                    uint32_t
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG8__READ                                 0xffffffffU

#endif /* __EMAC_DESIGNCFG_DEBUG8_MACRO__ */


/* macros for emac_designcfg_debug8 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG8__NUM                                       1

/* macros for emac_designcfg_debug9 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG9__NUM                                       1

/* macros for emac_designcfg_debug10 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG10__NUM                                      1

/* macros for emac_designcfg_debug11 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG11__NUM                                      1

/* macros for BlueprintGlobalNameSpace::emac_designcfg_debug12 */
#ifndef __EMAC_REGS__EMAC_DESIGNCFG_DEBUG12_MACRO__
#define __EMAC_REGS__EMAC_DESIGNCFG_DEBUG12_MACRO__

/* macros for field gem_num_cb_streams */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__SHIFT                     0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__WIDTH                     8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__MASK            0x000000ffU
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__RESET                     2
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_NUM_CB_STREAMS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)

/* macros for field gem_cb_history_len */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__SHIFT                     8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__WIDTH                     8
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__MASK            0x0000ff00U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__RESET                    64
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_CB_HISTORY_LEN__READ(src) \
                    (((uint32_t)(src)\
                    & 0x0000ff00U) >> 8)

/* macros for field gem_has_cb */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__SHIFT                            16
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__WIDTH                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__MASK                    0x00010000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__RESET                             1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__READ(src) \
                    (((uint32_t)(src)\
                    & 0x00010000U) >> 16)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(1) << 16)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_CB__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00010000U) | ((uint32_t)(0) << 16)

/* macros for field emac_rx_pbuf_addr */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__SHIFT                     17
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__WIDTH                      4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__MASK             0x001e0000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__RESET                     11
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_RX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x001e0000U) >> 17)

/* macros for field emac_tx_pbuf_addr */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__SHIFT                     21
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__WIDTH                      4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__MASK             0x01e00000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__RESET                     11
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__EMAC_TX_PBUF_ADDR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x01e00000U) >> 21)

/* macros for field gem_has_802p3_br */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__SHIFT                      25
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__WIDTH                       1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__MASK              0x02000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__RESET                       1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__READ(src) \
                    (((uint32_t)(src)\
                    & 0x02000000U) >> 25)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(1) << 25)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HAS_802P3_BR__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x02000000U) | ((uint32_t)(0) << 25)

/* macros for field gem_high_speed */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__SHIFT                        26
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__WIDTH                         1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__MASK                0x04000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__RESET                         1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__READ(src) \
                    (((uint32_t)(src)\
                    & 0x04000000U) >> 26)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(1) << 26)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_HIGH_SPEED__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x04000000U) | ((uint32_t)(0) << 26)

/* macros for field gem_vm */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__SHIFT                                27
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__WIDTH                                 1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__MASK                        0x08000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__RESET                                 1
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__READ(src) \
                    (((uint32_t)(src)\
                    & 0x08000000U) >> 27)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(1) << 27)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__GEM_VM__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x08000000U) | ((uint32_t)(0) << 27)

/* macros for field reserved_31_28 */
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__RESERVED_31_28__SHIFT                        28
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__RESERVED_31_28__WIDTH                         4
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__RESERVED_31_28__MASK                0xf0000000U
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__RESERVED_31_28__RESET                         0
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__RESERVED_31_28__READ(src) \
                    (((uint32_t)(src)\
                    & 0xf0000000U) >> 28)
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__TYPE                                   uint32_t
#define EMAC_REGS__EMAC_DESIGNCFG_DEBUG12__READ                                0xffffffffU

#endif /* __EMAC_DESIGNCFG_DEBUG12_MACRO__ */


/* macros for emac_designcfg_debug12 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG12__NUM                                      1

/* macros for emac_designcfg_debug13 */
#define EMAC_REGS__INST_EMAC_DESIGNCFG_DEBUG13__NUM                                      1

/* macros for BlueprintGlobalNameSpace::emac_axi_qos_cfg */
#ifndef __EMAC_REGS__EMAC_AXI_QOS_CFG_MACRO__
#define __EMAC_REGS__EMAC_AXI_QOS_CFG_MACRO__

/* macros for field emac_data_qos */
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__SHIFT                                0
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__WIDTH                                4
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__MASK                       0x0000000fU
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__RESET                                0
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DATA_QOS__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field emac_descr_qos */
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__SHIFT                               4
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__WIDTH                               4
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__MASK                      0x000000f0U
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__RESET                               0
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__EMAC_DESCR_QOS__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__EMAC_AXI_QOS_CFG__RESERVED_31_8__SHIFT                                8
#define EMAC_REGS__EMAC_AXI_QOS_CFG__RESERVED_31_8__WIDTH                               24
#define EMAC_REGS__EMAC_AXI_QOS_CFG__RESERVED_31_8__MASK                       0xffffff00U
#define EMAC_REGS__EMAC_AXI_QOS_CFG__RESERVED_31_8__RESET                                0
#define EMAC_REGS__EMAC_AXI_QOS_CFG__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__EMAC_AXI_QOS_CFG__TYPE                                         uint32_t
#define EMAC_REGS__EMAC_AXI_QOS_CFG__READ                                      0xffffffffU
#define EMAC_REGS__EMAC_AXI_QOS_CFG__WRITE                                     0xffffffffU

#endif /* __EMAC_AXI_QOS_CFG_MACRO__ */


/* macros for emac_axi_qos_cfg */
#define EMAC_REGS__INST_EMAC_AXI_QOS_CFG__NUM                                            1

/* macros for emac_spec_add5_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD5_BOTTOM__NUM                                       1

/* macros for emac_spec_add5_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD5_TOP__NUM                                          1

/* macros for emac_spec_add6_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD6_BOTTOM__NUM                                       1

/* macros for emac_spec_add6_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD6_TOP__NUM                                          1

/* macros for emac_spec_add7_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD7_BOTTOM__NUM                                       1

/* macros for emac_spec_add7_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD7_TOP__NUM                                          1

/* macros for emac_spec_add8_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD8_BOTTOM__NUM                                       1

/* macros for emac_spec_add8_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD8_TOP__NUM                                          1

/* macros for emac_spec_add9_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD9_BOTTOM__NUM                                       1

/* macros for emac_spec_add9_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD9_TOP__NUM                                          1

/* macros for emac_spec_add10_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD10_BOTTOM__NUM                                      1

/* macros for emac_spec_add10_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD10_TOP__NUM                                         1

/* macros for emac_spec_add11_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD11_BOTTOM__NUM                                      1

/* macros for emac_spec_add11_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD11_TOP__NUM                                         1

/* macros for emac_spec_add12_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD12_BOTTOM__NUM                                      1

/* macros for emac_spec_add12_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD12_TOP__NUM                                         1

/* macros for emac_spec_add13_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD13_BOTTOM__NUM                                      1

/* macros for emac_spec_add13_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD13_TOP__NUM                                         1

/* macros for emac_spec_add14_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD14_BOTTOM__NUM                                      1

/* macros for emac_spec_add14_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD14_TOP__NUM                                         1

/* macros for emac_spec_add15_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD15_BOTTOM__NUM                                      1

/* macros for emac_spec_add15_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD15_TOP__NUM                                         1

/* macros for emac_spec_add16_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD16_BOTTOM__NUM                                      1

/* macros for emac_spec_add16_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD16_TOP__NUM                                         1

/* macros for emac_spec_add17_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD17_BOTTOM__NUM                                      1

/* macros for emac_spec_add17_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD17_TOP__NUM                                         1

/* macros for emac_spec_add18_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD18_BOTTOM__NUM                                      1

/* macros for emac_spec_add18_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD18_TOP__NUM                                         1

/* macros for emac_spec_add19_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD19_BOTTOM__NUM                                      1

/* macros for emac_spec_add19_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD19_TOP__NUM                                         1

/* macros for emac_spec_add20_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD20_BOTTOM__NUM                                      1

/* macros for emac_spec_add20_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD20_TOP__NUM                                         1

/* macros for emac_spec_add21_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD21_BOTTOM__NUM                                      1

/* macros for emac_spec_add21_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD21_TOP__NUM                                         1

/* macros for emac_spec_add22_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD22_BOTTOM__NUM                                      1

/* macros for emac_spec_add22_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD22_TOP__NUM                                         1

/* macros for emac_spec_add23_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD23_BOTTOM__NUM                                      1

/* macros for emac_spec_add23_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD23_TOP__NUM                                         1

/* macros for emac_spec_add24_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD24_BOTTOM__NUM                                      1

/* macros for emac_spec_add24_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD24_TOP__NUM                                         1

/* macros for emac_spec_add25_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD25_BOTTOM__NUM                                      1

/* macros for emac_spec_add25_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD25_TOP__NUM                                         1

/* macros for emac_spec_add26_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD26_BOTTOM__NUM                                      1

/* macros for emac_spec_add26_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD26_TOP__NUM                                         1

/* macros for emac_spec_add27_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD27_BOTTOM__NUM                                      1

/* macros for emac_spec_add27_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD27_TOP__NUM                                         1

/* macros for emac_spec_add28_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD28_BOTTOM__NUM                                      1

/* macros for emac_spec_add28_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD28_TOP__NUM                                         1

/* macros for emac_spec_add29_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD29_BOTTOM__NUM                                      1

/* macros for emac_spec_add29_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD29_TOP__NUM                                         1

/* macros for emac_spec_add30_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD30_BOTTOM__NUM                                      1

/* macros for emac_spec_add30_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD30_TOP__NUM                                         1

/* macros for emac_spec_add31_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD31_BOTTOM__NUM                                      1

/* macros for emac_spec_add31_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD31_TOP__NUM                                         1

/* macros for emac_spec_add32_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD32_BOTTOM__NUM                                      1

/* macros for emac_spec_add32_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD32_TOP__NUM                                         1

/* macros for emac_spec_add33_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD33_BOTTOM__NUM                                      1

/* macros for emac_spec_add33_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD33_TOP__NUM                                         1

/* macros for emac_spec_add34_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD34_BOTTOM__NUM                                      1

/* macros for emac_spec_add34_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD34_TOP__NUM                                         1

/* macros for emac_spec_add35_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD35_BOTTOM__NUM                                      1

/* macros for emac_spec_add35_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD35_TOP__NUM                                         1

/* macros for emac_spec_add36_bottom */
#define EMAC_REGS__INST_EMAC_SPEC_ADD36_BOTTOM__NUM                                      1

/* macros for emac_spec_add36_top */
#define EMAC_REGS__INST_EMAC_SPEC_ADD36_TOP__NUM                                         1

/* macros for BlueprintGlobalNameSpace::emac_cbs_control */
#ifndef __EMAC_REGS__EMAC_CBS_CONTROL_MACRO__
#define __EMAC_REGS__EMAC_CBS_CONTROL_MACRO__

/* macros for field cbs_enable_queue_a */
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__SHIFT                           0
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__WIDTH                           1
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__MASK                  0x00000001U
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__RESET                           0
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000001U)
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | ((uint32_t)(src) &\
                    0x00000001U)
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000001U)))
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__SET(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(1)
#define EMAC_REGS__EMAC_CBS_CONTROL__CBS_ENABLE_QUEUE_A__CLR(dst) \
                    (dst) = ((dst) &\
                    ~0x00000001U) | (uint32_t)(0)

/* macros for field reserved_31_1 */
#define EMAC_REGS__EMAC_CBS_CONTROL__RESERVED_31_1__SHIFT                                1
#define EMAC_REGS__EMAC_CBS_CONTROL__RESERVED_31_1__WIDTH                               31
#define EMAC_REGS__EMAC_CBS_CONTROL__RESERVED_31_1__MASK                       0xfffffffeU
#define EMAC_REGS__EMAC_CBS_CONTROL__RESERVED_31_1__RESET                                0
#define EMAC_REGS__EMAC_CBS_CONTROL__RESERVED_31_1__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffeU) >> 1)
#define EMAC_REGS__EMAC_CBS_CONTROL__TYPE                                         uint32_t
#define EMAC_REGS__EMAC_CBS_CONTROL__READ                                      0xffffffffU
#define EMAC_REGS__EMAC_CBS_CONTROL__WRITE                                     0xffffffffU

#endif /* __EMAC_CBS_CONTROL_MACRO__ */


/* macros for emac_cbs_control */
#define EMAC_REGS__INST_EMAC_CBS_CONTROL__NUM                                            1

/* macros for emac_cbs_idleslope_q_a */
#define EMAC_REGS__INST_EMAC_CBS_IDLESLOPE_Q_A__NUM                                      1

/* macros for emac_cbs_idleslope_q_b */
#define EMAC_REGS__INST_EMAC_CBS_IDLESLOPE_Q_B__NUM                                      1

/* macros for emac_upper_tx_q_base_addr */
#define EMAC_REGS__INST_EMAC_UPPER_TX_Q_BASE_ADDR__NUM                                   1

/* macros for emac_tx_bd_control */
#define EMAC_REGS__INST_EMAC_TX_BD_CONTROL__NUM                                          1

/* macros for emac_rx_bd_control */
#define EMAC_REGS__INST_EMAC_RX_BD_CONTROL__NUM                                          1

/* macros for emac_upper_rx_q_base_addr */
#define EMAC_REGS__INST_EMAC_UPPER_RX_Q_BASE_ADDR__NUM                                   1

/* macros for emac_axi_host_arbitration */
#define EMAC_REGS__INST_EMAC_AXI_HOST_ARBITRATION__NUM                                   1

/* macros for emac_wd_counter */
#define EMAC_REGS__INST_EMAC_WD_COUNTER__NUM                                             1

/* macros for emac_wd_axi_tx_full_thresh0 */
#define EMAC_REGS__INST_EMAC_WD_AXI_TX_FULL_THRESH0__NUM                                 1

/* macros for emac_wd_axi_tx_full_thresh1 */
#define EMAC_REGS__INST_EMAC_WD_AXI_TX_FULL_THRESH1__NUM                                 1

/* macros for emac_screening_type_1_register */
#define EMAC_REGS__INST_EMAC_SCREENING_TYPE_1_REGISTER__NUM                              1

/* macros for emac_screening_type_2_register_0 */
#define EMAC_REGS__INST_EMAC_SCREENING_TYPE_2_REGISTER_0__NUM                            1

/* macros for emac_screening_type_2_register_1 */
#define EMAC_REGS__INST_EMAC_SCREENING_TYPE_2_REGISTER_1__NUM                            1

/* macros for BlueprintGlobalNameSpace::emac_tx_sched_ctrl */
#ifndef __EMAC_REGS__EMAC_TX_SCHED_CTRL_MACRO__
#define __EMAC_REGS__EMAC_TX_SCHED_CTRL_MACRO__

/* macros for field tx_sched */
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__SHIFT                                   0
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__WIDTH                                   2
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__MASK                          0x00000003U
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__RESET                                   0
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__READ(src) ((uint32_t)(src) & 0x00000003U)
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000003U)
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000003U) | ((uint32_t)(src) &\
                    0x00000003U)
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TX_SCHED__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000003U)))

/* macros for field reserved_31_2 */
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__RESERVED_31_2__SHIFT                              2
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__RESERVED_31_2__WIDTH                             30
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__RESERVED_31_2__MASK                     0xfffffffcU
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__RESERVED_31_2__RESET                              0
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__RESERVED_31_2__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffffcU) >> 2)
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__TYPE                                       uint32_t
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__READ                                    0xffffffffU
#define EMAC_REGS__EMAC_TX_SCHED_CTRL__WRITE                                   0xffffffffU

#endif /* __EMAC_TX_SCHED_CTRL_MACRO__ */


/* macros for emac_tx_sched_ctrl */
#define EMAC_REGS__INST_EMAC_TX_SCHED_CTRL__NUM                                          1

/* macros for BlueprintGlobalNameSpace::emac_bw_rate_limit */
#ifndef __EMAC_REGS__EMAC_BW_RATE_LIMIT_MACRO__
#define __EMAC_REGS__EMAC_BW_RATE_LIMIT_MACRO__

/* macros for field emac_dwrr_ets_weight */
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__SHIFT                       0
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__WIDTH                       8
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__MASK              0x000000ffU
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__RESET                       0
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__READ(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x000000ffU)
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000ffU) | ((uint32_t)(src) &\
                    0x000000ffU)
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__EMAC_DWRR_ETS_WEIGHT__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x000000ffU)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__RESERVED_31_8__SHIFT                              8
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__RESERVED_31_8__WIDTH                             24
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__RESERVED_31_8__MASK                     0xffffff00U
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__RESERVED_31_8__RESET                              0
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__TYPE                                       uint32_t
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__READ                                    0xffffffffU
#define EMAC_REGS__EMAC_BW_RATE_LIMIT__WRITE                                   0xffffffffU

#endif /* __EMAC_BW_RATE_LIMIT_MACRO__ */


/* macros for emac_bw_rate_limit */
#define EMAC_REGS__INST_EMAC_BW_RATE_LIMIT__NUM                                          1

/* macros for BlueprintGlobalNameSpace::emac_tx_q_seg_alloc_q_lower */
#ifndef __EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER_MACRO__
#define __EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER_MACRO__

/* macros for field segment_alloc */
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__SHIFT                     0
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__WIDTH                     3
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__MASK            0x00000007U
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__RESET                     0
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x00000007U)
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x00000007U) | ((uint32_t)(src) &\
                    0x00000007U)
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__SEGMENT_ALLOC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x00000007U)))

/* macros for field reserved_31_3 */
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_3__SHIFT                     3
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_3__WIDTH                    29
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_3__MASK            0xfffffff8U
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_3__RESET                     0
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__RESERVED_31_3__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffffff8U) >> 3)
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__TYPE                              uint32_t
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__READ                           0xffffffffU
#define EMAC_REGS__EMAC_TX_Q_SEG_ALLOC_Q_LOWER__WRITE                          0xffffffffU

#endif /* __EMAC_TX_Q_SEG_ALLOC_Q_LOWER_MACRO__ */


/* macros for emac_tx_q_seg_alloc_q_lower */
#define EMAC_REGS__INST_EMAC_TX_Q_SEG_ALLOC_Q_LOWER__NUM                                 1

/* macros for emac_type2_compare_0_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_0_WORD_0__NUM                                 1

/* macros for emac_type2_compare_0_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_0_WORD_1__NUM                                 1

/* macros for emac_type2_compare_1_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_1_WORD_0__NUM                                 1

/* macros for emac_type2_compare_1_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_1_WORD_1__NUM                                 1

/* macros for emac_type2_compare_2_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_2_WORD_0__NUM                                 1

/* macros for emac_type2_compare_2_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_2_WORD_1__NUM                                 1

/* macros for emac_type2_compare_3_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_3_WORD_0__NUM                                 1

/* macros for emac_type2_compare_3_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_3_WORD_1__NUM                                 1

/* macros for emac_type2_compare_4_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_4_WORD_0__NUM                                 1

/* macros for emac_type2_compare_4_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_4_WORD_1__NUM                                 1

/* macros for emac_type2_compare_5_word_0 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_5_WORD_0__NUM                                 1

/* macros for emac_type2_compare_5_word_1 */
#define EMAC_REGS__INST_EMAC_TYPE2_COMPARE_5_WORD_1__NUM                                 1

/* macros for BlueprintGlobalNameSpace::enst_start_time_q0 */
#ifndef __EMAC_REGS__ENST_START_TIME_Q0_MACRO__
#define __EMAC_REGS__ENST_START_TIME_Q0_MACRO__

/* macros for field start_time_nsec */
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__SHIFT                            0
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__WIDTH                           30
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__MASK                   0x3fffffffU
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__RESET                            0
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__READ(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x3fffffffU) | ((uint32_t)(src) &\
                    0x3fffffffU)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_NSEC__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x3fffffffU)))

/* macros for field start_time_sec */
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__SHIFT                            30
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__WIDTH                             2
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__MASK                    0xc0000000U
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__RESET                             0
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__READ(src) \
                    (((uint32_t)(src)\
                    & 0xc0000000U) >> 30)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__WRITE(src) \
                    (((uint32_t)(src)\
                    << 30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0xc0000000U) | (((uint32_t)(src) <<\
                    30) & 0xc0000000U)
#define EMAC_REGS__ENST_START_TIME_Q0__START_TIME_SEC__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 30) & ~0xc0000000U)))
#define EMAC_REGS__ENST_START_TIME_Q0__TYPE                                       uint32_t
#define EMAC_REGS__ENST_START_TIME_Q0__READ                                    0xffffffffU
#define EMAC_REGS__ENST_START_TIME_Q0__WRITE                                   0xffffffffU

#endif /* __ENST_START_TIME_Q0_MACRO__ */


/* macros for emac_enst_start_time */
#define EMAC_REGS__INST_EMAC_ENST_START_TIME__NUM                                        1

/* macros for BlueprintGlobalNameSpace::enst_on_time_q0 */
#ifndef __EMAC_REGS__ENST_ON_TIME_Q0_MACRO__
#define __EMAC_REGS__ENST_ON_TIME_Q0_MACRO__

/* macros for field on_time */
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__SHIFT                                       0
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__WIDTH                                      17
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__MASK                              0x0001ffffU
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__RESET                                 0x1FFFF
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__READ(src)     ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__WRITE(src)    ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_ON_TIME_Q0__ON_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_ON_TIME_Q0__RESERVED_31_17__SHIFT                               17
#define EMAC_REGS__ENST_ON_TIME_Q0__RESERVED_31_17__WIDTH                               15
#define EMAC_REGS__ENST_ON_TIME_Q0__RESERVED_31_17__MASK                       0xfffe0000U
#define EMAC_REGS__ENST_ON_TIME_Q0__RESERVED_31_17__RESET                                0
#define EMAC_REGS__ENST_ON_TIME_Q0__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_ON_TIME_Q0__TYPE                                          uint32_t
#define EMAC_REGS__ENST_ON_TIME_Q0__READ                                       0xffffffffU
#define EMAC_REGS__ENST_ON_TIME_Q0__WRITE                                      0xffffffffU

#endif /* __ENST_ON_TIME_Q0_MACRO__ */


/* macros for emac_enst_on_time */
#define EMAC_REGS__INST_EMAC_ENST_ON_TIME__NUM                                           1

/* macros for BlueprintGlobalNameSpace::enst_off_time_q0 */
#ifndef __EMAC_REGS__ENST_OFF_TIME_Q0_MACRO__
#define __EMAC_REGS__ENST_OFF_TIME_Q0_MACRO__

/* macros for field off_time */
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__SHIFT                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__WIDTH                                    17
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__MASK                            0x0001ffffU
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__RESET                                     0
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__READ(src)   ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__WRITE(src)  ((uint32_t)(src) & 0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0001ffffU) | ((uint32_t)(src) &\
                    0x0001ffffU)
#define EMAC_REGS__ENST_OFF_TIME_Q0__OFF_TIME__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0001ffffU)))

/* macros for field reserved_31_17 */
#define EMAC_REGS__ENST_OFF_TIME_Q0__RESERVED_31_17__SHIFT                              17
#define EMAC_REGS__ENST_OFF_TIME_Q0__RESERVED_31_17__WIDTH                              15
#define EMAC_REGS__ENST_OFF_TIME_Q0__RESERVED_31_17__MASK                      0xfffe0000U
#define EMAC_REGS__ENST_OFF_TIME_Q0__RESERVED_31_17__RESET                               0
#define EMAC_REGS__ENST_OFF_TIME_Q0__RESERVED_31_17__READ(src) \
                    (((uint32_t)(src)\
                    & 0xfffe0000U) >> 17)
#define EMAC_REGS__ENST_OFF_TIME_Q0__TYPE                                         uint32_t
#define EMAC_REGS__ENST_OFF_TIME_Q0__READ                                      0xffffffffU
#define EMAC_REGS__ENST_OFF_TIME_Q0__WRITE                                     0xffffffffU

#endif /* __ENST_OFF_TIME_Q0_MACRO__ */


/* macros for emac_enst_off_time */
#define EMAC_REGS__INST_EMAC_ENST_OFF_TIME__NUM                                          1

/* macros for emac_enst_control */
#define EMAC_REGS__INST_EMAC_ENST_CONTROL__NUM                                           1

/* macros for emac_frer_timeout */
#define EMAC_REGS__INST_EMAC_FRER_TIMEOUT__NUM                                           1

/* macros for emac_frer_red_tag */
#define EMAC_REGS__INST_EMAC_FRER_RED_TAG__NUM                                           1

/* macros for emac_frer_control_1_a */
#define EMAC_REGS__INST_EMAC_FRER_CONTROL_1_A__NUM                                       1

/* macros for emac_frer_control_1_b */
#define EMAC_REGS__INST_EMAC_FRER_CONTROL_1_B__NUM                                       1

/* macros for emac_frer_statistics_1_a */
#define EMAC_REGS__INST_EMAC_FRER_STATISTICS_1_A__NUM                                    1

/* macros for emac_frer_statistics_1_b */
#define EMAC_REGS__INST_EMAC_FRER_STATISTICS_1_B__NUM                                    1

/* macros for emac_frer_control_2_a */
#define EMAC_REGS__INST_EMAC_FRER_CONTROL_2_A__NUM                                       1

/* macros for emac_frer_control_2_b */
#define EMAC_REGS__INST_EMAC_FRER_CONTROL_2_B__NUM                                       1

/* macros for emac_frer_statistics_2_a */
#define EMAC_REGS__INST_EMAC_FRER_STATISTICS_2_A__NUM                                    1

/* macros for emac_frer_statistics_2_b */
#define EMAC_REGS__INST_EMAC_FRER_STATISTICS_2_B__NUM                                    1

/* macros for BlueprintGlobalNameSpace::emac_tx_descr_rd_buf_ctl */
#ifndef __EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL_MACRO__
#define __EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL_MACRO__

/* macros for field emac_high_watermark */
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__SHIFT                  0
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__WIDTH                  4
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__MASK         0x0000000fU
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__RESET                  4
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field emac_low_watermark */
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__SHIFT                   4
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__WIDTH                   4
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__MASK          0x000000f0U
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__RESET                   4
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__RESERVED_31_8__SHIFT                        8
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__RESERVED_31_8__WIDTH                       24
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__RESERVED_31_8__MASK               0xffffff00U
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__RESERVED_31_8__RESET                        0
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__TYPE                                 uint32_t
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__READ                              0xffffffffU
#define EMAC_REGS__EMAC_TX_DESCR_RD_BUF_CTL__WRITE                             0xffffffffU

#endif /* __EMAC_TX_DESCR_RD_BUF_CTL_MACRO__ */


/* macros for emac_tx_descr_rd_buf_ctl */
#define EMAC_REGS__INST_EMAC_TX_DESCR_RD_BUF_CTL__NUM                                    1

/* macros for BlueprintGlobalNameSpace::emac_rx_descr_rd_buf_ctl */
#ifndef __EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL_MACRO__
#define __EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL_MACRO__

/* macros for field emac_high_watermark */
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__SHIFT                  0
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__WIDTH                  4
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__MASK         0x0000000fU
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__RESET                  4
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__READ(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__WRITE(src) \
                    ((uint32_t)(src)\
                    & 0x0000000fU)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x0000000fU) | ((uint32_t)(src) &\
                    0x0000000fU)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_HIGH_WATERMARK__VERIFY(src) \
                    (!(((uint32_t)(src)\
                    & ~0x0000000fU)))

/* macros for field emac_low_watermark */
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__SHIFT                   4
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__WIDTH                   4
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__MASK          0x000000f0U
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__RESET                   4
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__READ(src) \
                    (((uint32_t)(src)\
                    & 0x000000f0U) >> 4)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__WRITE(src) \
                    (((uint32_t)(src)\
                    << 4) & 0x000000f0U)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__MODIFY(dst, src) \
                    (dst) = ((dst) &\
                    ~0x000000f0U) | (((uint32_t)(src) <<\
                    4) & 0x000000f0U)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__EMAC_LOW_WATERMARK__VERIFY(src) \
                    (!((((uint32_t)(src)\
                    << 4) & ~0x000000f0U)))

/* macros for field reserved_31_8 */
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__RESERVED_31_8__SHIFT                        8
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__RESERVED_31_8__WIDTH                       24
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__RESERVED_31_8__MASK               0xffffff00U
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__RESERVED_31_8__RESET                        0
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__RESERVED_31_8__READ(src) \
                    (((uint32_t)(src)\
                    & 0xffffff00U) >> 8)
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__TYPE                                 uint32_t
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__READ                              0xffffffffU
#define EMAC_REGS__EMAC_RX_DESCR_RD_BUF_CTL__WRITE                             0xffffffffU

#endif /* __EMAC_RX_DESCR_RD_BUF_CTL_MACRO__ */


/* macros for emac_rx_descr_rd_buf_ctl */
#define EMAC_REGS__INST_EMAC_RX_DESCR_RD_BUF_CTL__NUM                                    1

/* macros for emac_gem_axi_xacts_rd */
#define EMAC_REGS__INST_EMAC_GEM_AXI_XACTS_RD__NUM                                       1

/* macros for emac_gem_axi_xacts_wr */
#define EMAC_REGS__INST_EMAC_GEM_AXI_XACTS_WR__NUM                                       1

/* macros for emac_rx_q0_flush */
#define EMAC_REGS__INST_EMAC_RX_Q0_FLUSH__NUM                                            1

/* macros for emac_scr2_reg0_rate_limit */
#define EMAC_REGS__INST_EMAC_SCR2_REG0_RATE_LIMIT__NUM                                   1

/* macros for emac_scr2_reg1_rate_limit */
#define EMAC_REGS__INST_EMAC_SCR2_REG1_RATE_LIMIT__NUM                                   1

/* macros for emac_scr2_rate_status */
#define EMAC_REGS__INST_EMAC_SCR2_RATE_STATUS__NUM                                       1

/* macros for emac_q0_control */
#define EMAC_REGS__INST_EMAC_Q0_CONTROL__NUM                                             1

/* macros for emac_q0_status */
#define EMAC_REGS__INST_EMAC_Q0_STATUS__NUM                                              1

#endif /* __REG_EMAC_REGS_MACRO_H__ */
